Data Sheet
SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (SN54S373, SN54S374, SN74S373, SN74S374)
PARAMETER
TEST CONDITIONS
†
MIN
TYP
‡
MAX UNIT
V
IH
2 V
V
IL
0.8 V
V
IK
V
CC
= MIN, I
I
= –18 mA –1.2 V
V
OH
SN54S’
V
CC
= MIN
V
IH
=2V
V
IL
=08V
I
OH
= MAX
2.4 3.4
V
V
OH
SN74S’
V
CC
=
MIN
,
V
IH
=
2
V
,
V
IL
=
0
.
8
V
,
I
OH
=
MAX
2.4 3.1
V
V
OL
V
CC
= MIN, V
IH
= 2 V, V
IL
= 0.8 V, I
OL
= 20 mA 0.5 V
I
OZH
V
CC
= MAX, V
IH
= 2 V, V
O
= 2.4 V 50 A
I
OZL
V
CC
= MAX, V
IH
= 2 V, V
O
= 0.5 V –50 A
I
I
V
CC
= MAX, V
I
= 5.5 V 1 mA
I
IH
V
CC
= MAX, V
I
= 2.7 V 50 A
I
IL
V
CC
= MAX, V
I
= 0.5 V –250 A
I
OS
§
V
CC
= MAX –40 –100 mA
Outputs high 160
’S373
Outputs low 160
Outputs disabled 190
I
CC
V
CC
= MAX
Outputs high 110
mA
’
S374
Outputs low 140
’S374
Outputs disabled 160
CLK and OC at 4 V, D inputs at 0 V 180
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡
All typical values are at V
CC
= 5 V, T
A
= 25°C.
§
Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second.
switching characteristics, V
CC
= 5 V, T
A
= 25°C (see Figure 2)
PARAMETER
FROM TO
TEST CONDITIONS
’S373 ’S374
UNIT
PARAMETER
(INPUT) (OUTPUT)
TEST
CONDITIONS
MIN TYP MAX MIN TYP MAX
UNIT
f
max
R
L
= 280 Ω C
L
= 15 pF,
See Note 3
75 100 MHz
t
PLH
Data
Any Q
R
L
= 280 Ω C
L
= 15 pF,
7 12
ns
t
PHL
Data
Any
Q
L L
,
See Note 3
7 12
ns
t
PLH
CorCLK
Any Q
R
L
= 280 Ω C
L
= 15 pF,
7 14 8 15
ns
t
PHL
C
or
CLK
Any
Q
L L
,
See Note 3
12 18 11 17
ns
t
PZH
OC
Any Q
R
L
= 280 Ω C
L
= 15 pF,
8 15 8 15
ns
t
PZL
OC
Any
Q
L L
,
See Note 3
11 18 11 18
ns
t
PHZ
OC
Any Q
R
L
= 280 Ω C
L
=5
p
F
6 9 5 9
ns
t
PLZ
OC
Any
Q
R
L
=
280
Ω C
L
=
5
pF
8 12 7 12
ns
NOTE 3. Maximum clock frequency is tested with all outputs loaded.
f
max
= maximum clock frequency
t
PLH
= propagation delay time, low-to-high-level output
t
PHL
= propagation delay time, high-to-low-level output
t
PZH
= output enable time to high level
t
PZL
= output enable time to low level
t
PHZ
= output disable time from high level
t
PLZ
= output disable time from low level