Data Sheet

ManualsBrandsUnbranded ManualsActive ComponentsSN74LV123AD Logic IC - Multivibrator Monostable 13 ns SOIC 16 N

SN54LV123A . . . J OR W PACKAGE

SN74LV123A . . . D, DB, DGV, NS,

OR PW PACKAGE

(TOP VIEW)

SN54LV123A . . . FK PACKAGE

(TOP VIEW)

1CLR

ext

GND

ext

2CLR

3 2 1 20 19

9 10 11 12 13

ext

2CLR

1CLR

ext

GND

NC − No internal connection

ext

SN74LV123A . . . RGY PACKAGE

(TOP VIEW)

1 16

8 9

ext

2CLR

1CLR

ext

GND

SN54LV123A, SN74LV123A

www.ti.com

SCLS393P –APRIL 1998–REVISED OCTOBER 2013

DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATORS

WITH SCHMITT-TRIGGER INPUTS

Check for Samples: SN54LV123A, SN74LV123A

FEATURES

DESCRIPTION

The 'LV123A devices are dual retriggerable

• 2-V to 5.5-V V

Operation

monostable multivibrators designed for 2-V to 5.5-V

• Max t

of 11 ns at 5 V

operation.

• Typical V

OLP

(Output Ground Bounce)

These edge-triggered multivibrators feature output

<0.8 V at V

= 3.3 V, T

= 25 ° C

pulse-duration control by three methods. In the first

• Typical V

OHV

(Output V

Undershoot)

method, the A input is low, and the B input goes high.

>2.3 V at V

= 3.3 V, T

= 25 ° C

In the second method, the B input is high, and the A

input goes low. In the third method, the A input is low,

• Support Mixed-Mode Voltage Operation on All

the B input is high, and the clear (CLR) input goes

Ports

high.

• Schmitt-Trigger Circuitry on A, B, and CLR

The output pulse duration is programmable by

Inputs for Slow Input Transition Rates

selecting external resistance and capacitance values.

• Edge Triggered From Active-High or Active-

The external timing capacitor must be connected

Low Gated Logic Inputs

between C

ext

and R

ext

(positive) and an external

• I

off

Supports Partial-Power-Down Mode

resistor connected between R

ext

and V

. To

Operation

obtain variable pulse durations, connect an external

variable resistance between R

ext

and V

. The

• Retriggerable for Very Long Output Pulses, up

output pulse duration also can be reduced by taking

to 100% Duty Cycle

CLR low.

• Overriding Clear Terminates Output Pulse

• Glitch-Free Power-Up Reset on Outputs

• ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

• Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class 11

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (31 pages)

PAGE 1
SN54LV123A, SN74LV123A www.ti.com SCLS393P – APRIL 1998 – REVISED OCTOBER 2013 DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS Check for Samples: SN54LV123A, SN74LV123A FEATURES DESCRIPTION • • • The 'LV123A devices are dual retriggerable monostable multivibrators designed for 2-V to 5.5-V VCC operation. • • • • • SN74LV123A . . . RGY PACKAGE (TOP VIEW) SN54LV123A . . . J OR W PACKAGE SN74LV123A . . .
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SN54LV123A, SN74LV123A SCLS393P – APRIL 1998 – REVISED OCTOBER 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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SN54LV123A, SN74LV123A www.ti.com SCLS393P – APRIL 1998 – REVISED OCTOBER 2013 Figure 2.
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SN54LV123A, SN74LV123A SCLS393P – APRIL 1998 – REVISED OCTOBER 2013 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature (unless otherwise noted) MIN MAX UNIT VCC Supply voltage range –0.5 7 V VI Input voltage range (2) –0.5 7 V VO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 7 V VO Output voltage range in the high or low state (2) –0.5 VCC + 0.
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SN54LV123A, SN74LV123A www.ti.com SCLS393P – APRIL 1998 – REVISED OCTOBER 2013 RECOMMENDED OPERATING CONDITIONS (1) SN54LV123A (2) VCC Supply voltage VCC = 2 V VIH High-level input voltage SN74LV123A MIN MAX 2 5.5 MIN MAX 2 5.5 1.5 1.5 VCC = 2.3 V to 2.7 V VCC × 0.7 VCC × 0.7 VCC = 3 V to 3.6 V VCC × 0.7 VCC × 0.7 VCC = 4.5 V to 5.5 V VCC × 0.7 VCC × 0.7 VCC = 2 V UNIT V V 0.5 0.5 VCC = 2.3 V to 2.7 V VCC × 0.3 VCC × 0.3 VCC = 3 V to 3.6 V VCC × 0.3 VCC × 0.
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SN54LV123A, SN74LV123A SCLS393P – APRIL 1998 – REVISED OCTOBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS –55°C to 125°C SN54LV123A (1) VCC MIN TYP VOH MAX MIN TYP VCC – 0.1 MAX VCC – 0.1 MIN TYP UNIT MAX VCC – 0.1 IOH = –50 μA 2 V to 5.5 V IOH = –2 mA 2.3 V 2 2 2 IOH = –6 mA 3V 2.48 2.48 2.48 4.5 V 3.
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SN54LV123A, SN74LV123A www.ti.com SCLS393P – APRIL 1998 – REVISED OCTOBER 2013 TIMING REQUIREMENTS over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 3) PARAMETER TEST CONDITIONS TA = 25°C MIN tw trr (1) (2) Pulse duration TYP –55°C to 125°C SN54LV123A (1) MIN MAX –40°C to 85°C SN74LV123A MIN CLR 5 5 5 A or B trigger 5 5 5 Cext = 100 pF See (2) 59 See (2) (2) Cext = 0.01 μF See (2) 1.
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SN54LV123A, SN74LV123A SCLS393P – APRIL 1998 – REVISED OCTOBER 2013 www.ti.com SWITCHING CHARACTERISTICS over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 3) PARAMETE R tpd tpd FROM (INPUT) TO (OUTPUT) A or B Q or Q CLR Q or Q CLR trigger Q or Q A or B Q or Q CLR Q or Q CLR trigger Q or Q (3) Δtw (1) (2) (3) (4) Q or Q (4) –40°C to 85°C SN74LV123A –40°C to 125°C SN74LV123A MIN TYP MAX MIN MAX MIN MAX 14.5 31.
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SN54LV123A, SN74LV123A www.ti.com SCLS393P – APRIL 1998 – REVISED OCTOBER 2013 SWITCHING CHARACTERISTICS over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 3) PARAMETER tpd tpd Δtw (1) (2) (3) (4) (3) –40°C to 85°C SN74LV123 A –40°C to 125°C SN74LV123A MIN TYP MAX MIN MAX MIN MAX A or B Q or Q 7.1 12 (2) 1 (2) 14 (2) 1 14 1 14 CLR Q or Q 6.5 9.4 (2) 1 (2) 11 (2) 1 11 1 11 12.
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SN54LV123A, SN74LV123A SCLS393P – APRIL 1998 – REVISED OCTOBER 2013 www.ti.
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SN54LV123A, SN74LV123A www.ti.com SCLS393P – APRIL 1998 – REVISED OCTOBER 2013 APPLICATION INFORMATION Operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. OUTPUT PULSE DURATION vs EXTERNAL TIMING CAPACITANCE 1.00E+07 VCC = 3 V TA = 25°C 1.00E+06 t w − Output Pulse Duration − ns t w − Output Pulse Duration − ns 1.00E+07 OUTPUT PULSE DURATION vs EXTERNAL TIMING CAPACITANCE RT = 1 MΩ 1.00E+05 RT = 100 kΩ 1.
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SN54LV123A, SN74LV123A SCLS393P – APRIL 1998 – REVISED OCTOBER 2013 www.ti.com 1.00E+09 VCC = 5 V TA = 25°C 1.00E+08 RT = 200k Ω t w − Output Pulse Duration − ns 1.00E+07 RT = 150k Ω 1.00E+06 RT = 80k Ω 1.00E+05 RT = 10k Ω 1.00E+04 RT = 5k Ω 1.00E+03 1.00E+02 RT = 1k Ω 1.00E+01 1.00E+00 1 102 10 103 104 105 106 107 CT − External Timing Capacitance − pF Figure 6.
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SN54LV123A, SN74LV123A www.ti.com SCLS393P – APRIL 1998 – REVISED OCTOBER 2013 MINIMUM TRIGGER TIME vs VCC CHARACTERISTICS OUTPUT PULSE-DURATION CONSTANT vs SUPPLY VOLTAGE 1.20 10.00 Output Pulse Duration Constant − K t rr − Minimum Retrigger Time − µs RT = 1 kΩ TA = 25°C CT = 0.01 µF 1.00 CT = 1000 pF 0.10 CT = 100 pF 1 2 3 4 5 1.10 CT = 1000 pF 1.05 6 CT = 0.01 µF 1.00 CT = 1 µF, CT = 0.1 µF 0.95 0.90 1.5 0.01 0 1.15 RT = 10 kΩ TA = 25°C tw = K × CT × RT 2 2.5 3 3.5 4 4.
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SN54LV123A, SN74LV123A SCLS393P – APRIL 1998 – REVISED OCTOBER 2013 www.ti.com Caution In Use To prevent malfunctions due to noise, connect a high-frequency capacitor between VCC and GND, and keep the wiring between the external components and Cext and Rext/Cext terminals as short as possible. Power-Down Considerations Large values of Cext can cause problems when powering down the 'LV123A devices because of the amount of energy stored in the capacitor.
PAGE 15
SN54LV123A, SN74LV123A www.ti.com SCLS393P – APRIL 1998 – REVISED OCTOBER 2013 Retriggering Data The minimum input retriggering time (tMIR) is the minimum time required after the initial signal before retriggering the input. After tMIR, the device retriggers the output. Experimentally, it also can be shown that to retrigger the output pulse, the two adjacent input signals should be tMIR apart, where tMIR = 0.30 × tw. The retrigger pulse duration is calculated as shown in Figure 13.
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SN54LV123A, SN74LV123A SCLS393P – APRIL 1998 – REVISED OCTOBER 2013 www.ti.com REVISION HISTORY Changes from Revision O (April 1998) to Revision P Page • Updated document to new TI datasheet format - no specification changes. ....................................................................... 1 • Removed Ordering Information table. ...................................................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com (4) 18-Oct-2013 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
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PACKAGE MATERIALS INFORMATION www.ti.com 5-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.6 2.5 12.0 16.0 Q1 SN74LV123ADBR SSOP DB 16 2000 330.0 16.4 8.2 SN74LV123ADGVR TVSOP DGV 16 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1 SN74LV123ADR SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 5-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LV123ADBR SSOP DB 16 2000 367.0 367.0 38.0 SN74LV123ADGVR TVSOP DGV 16 2000 367.0 367.0 35.0 SN74LV123ADR SOIC D 16 2500 364.0 364.0 27.0 SN74LV123ADRG4 SOIC D 16 2500 333.2 345.9 28.6 SN74LV123APWR TSSOP PW 16 2000 364.0 364.0 27.0 SN74LV123APWRG4 TSSOP PW 16 2000 367.0 367.0 35.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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