Data Sheet

ManualsBrandsUnbranded ManualsActive ComponentsLinear IC - Audio amplifier TAS5142DKD 2-channel (stereo) Class D HSSOP 36

www.ti.com

FEATURES

APPLICATIONS

DESCRIPTION

PVDD − Supply Voltage − V

100

110

120

0 4 8 12 16 20 24 28 32

− Output Power − W

8 Ω

4 Ω

= 75°C

THD+N @ 10%

6 Ω

G002

TAS5142

SLES126B – DECEMBER 2004 – REVISED MAY 2005

STEREO DIGITAL AMPLIFIER POWER STAGE

requires a simple passive LC demodulation filter to

deliver high-quality, high-efficiency audio amplification

• 2×100 W at 10% THD+N Into 4- Ω BTL

(1)

with proven EMI compliance. This device requires two

• 2×80 W at 10% THD+N Into 6- Ω BTL

power supplies, at 12 V for GVDD and VDD, and at

32 V for PVDD. The TAS5142 does not require

• 2×65 W at 10% THD+N Into 8- Ω BTL

power-up sequencing due to internal power-on reset.

• 4×40 W at 10% THD+N Into 3- Ω SE

The efficiency of this digital amplifier is greater than

• 4×30 W at 10% THD+N Into 4- Ω SE

90% into 6 Ω , which enables the use of smaller

• 1×160 W at 10% THD+N Into 3- Ω PBTL

power supplies and heatsinks.

• 1×200 W at 10% THD+N Into 2- Ω PBTL

(1)

The TAS5142 has an innovative protection system

integrated on-chip, safeguarding the device against a

• >100 dB SNR (A-Weighted)

wide range of fault conditions that could damage the

• <0.1% THD+N at 1 W

system. These safeguards are short-circuit protection,

• Two Thermally Enhanced Package Options:

overcurrent protection, undervoltage protection, and

– DKD (36-pin PSOP3)

overtemperature protection. The TAS5142 has a new

proprietary current-limiting circuit that reduces the

– DDV (44-pin HTSSOP)

possibility of device shutdown during high-level music

• High-Efficiency Power Stage (>90%) With

transients. A new programmable overcurrent detector

140-m Ω Output MOSFETs

allows the use of lower-cost inductors in the

• Power-On Reset for Protection on Power Up

demodulation output filter.

Without Any Power-Supply Sequencing

BTL OUTPUT POWER vs SUPPLY VOLTAGE

• Integrated Self-Protection Circuits Including

Undervoltage, Overtemperature, Overload,

Short Circuit

• Error Reporting

• EMI Compliant When Used With

Recommended System Design

• Intelligent Gate Drive

• Mini/Micro Audio System

• DVD Receiver

• Home Theater

The TAS5142 is a third-generation, high-perform-

ance, integrated stereo digital amplifier power stage

with an improved protection system. The TAS5142 is

capable of driving a 4- Ω bridge-tied load (BTL) at up

(1) It is not recommended to drive 200 W (total power) into the

to 100 W per channel with low integrated noise at the

DDV package continuously. For multichannel systems that

output, low THD+N performance, and low idle power

require two channels to be driven at full power with the

dissipation.

DDV package option, it is recommended to design the

system so that the two channels are in two separate

A low-cost, high-fidelity audio system can be built

devices.

using a TI chipset, comprising a modulator (e.g.,

PurePath Digital™

TAS5508) and the TAS5142. This system only

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PurePath Digital, PowerPad are trademarks of Texas Instruments.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (32 pages)

PAGE 1
TM TAS5142 www.ti.com SLES126B – DECEMBER 2004 – REVISED MAY 2005 STEREO DIGITAL AMPLIFIER POWER STAGE • • • • • • • • • • • • • • • • 2×100 W at 10% THD+N Into 4-Ω BTL (1) 2×80 W at 10% THD+N Into 6-Ω BTL 2×65 W at 10% THD+N Into 8-Ω BTL 4×40 W at 10% THD+N Into 3-Ω SE 4×30 W at 10% THD+N Into 4-Ω SE 1×160 W at 10% THD+N Into 3-Ω PBTL 1×200 W at 10% THD+N Into 2-Ω PBTL (1) >100 dB SNR (A-Weighted) <0.
PAGE 2
TAS5142 www.ti.com SLES126B – DECEMBER 2004 – REVISED MAY 2005 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
PAGE 3
TAS5142 www.ti.com SLES126B – DECEMBER 2004 – REVISED MAY 2005 GENERAL INFORMATION (continued) MODE Selection Pins for Both Packages MODE PINS (1) (2) PWM INPUT M3 M2 M1 0 0 0 2N 0 0 1 Reserved 0 1 0 1N (1) 0 1 1 1N (1) 1N (1) 1 0 0 1 0 1 1 1 0 1 1 1 (1) OUTPUT CONFIGURATION PROTECTION SCHEME 2 channels BTL output BTL mode (2) AD modulation 2 channels BTL output BTL mode (2) AD modulation 1 channel PBTL output PBTL mode. Only PWM_A input is used.
PAGE 4
TAS5142 www.ti.com SLES126B – DECEMBER 2004 – REVISED MAY 2005 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) TAS5142 VDD to AGND –0.3 V to 13.2 V GVDD_X to AGND –0.3 V to 13.2 V PVDD_X to GND_X (2) –0.3 V to 50 V OUT_X to GND_X (2) –0.3 V to 50 V BST_X to GND_X (2) –0.3 V to 63.2 V VREG to AGND –0.3 V to 4.2 V GND_X to GND –0.3 V to 0.3 V GND_X to AGND –0.3 V to 0.3 V GND to AGND –0.3 V to 0.3 V PWM_X, OC_ADJ, M1, M2, M3 to AGND –0.
PAGE 5
TAS5142 www.ti.com SLES126B – DECEMBER 2004 – REVISED MAY 2005 Terminal Functions TERMINAL NAME (1) DKD NO. DDV NO.
PAGE 6
TAS5142 www.ti.
PAGE 7
TAS5142 www.ti.com SLES126B – DECEMBER 2004 – REVISED MAY 2005 FUNCTIONAL BLOCK DIAGRAM VDD Undervoltage Protection OTW Internal Pullup Resistors to VREG SD M1 Protection and I/O Logic M2 M3 4 VREG VREG Power On Reset AGND Temp. Sense GND RESET_AB Overload Protection RESET_CD Isense OC_ADJ GVDD_D BST_D PVDD_D PWM_D PWM Rcv. Ctrl. Timing Gate Drive OUT_D BTL/PBTL−Configuration Pulldown Resistor GND_D GVDD_C BST_C PVDD_C PWM_C PWM Rcv. Ctrl.
PAGE 8
TAS5142 www.ti.com SLES126B – DECEMBER 2004 – REVISED MAY 2005 RECOMMENDED OPERATING CONDITIONS MIN TYP MAX UNIT PVDD_X Half-bridge supply DC supply voltage 0 32 34 V GVDD_X Supply for logic regulators and gate-drive circuitry DC supply voltage 10.8 12 13.2 V VDD Digital regulator input DC supply voltage 10.8 12 13.2 V 3 4 2 3 RL (BTL) RL (SE) Output filter: L = 10 µH, C = 470 nF.
PAGE 9
TAS5142 www.ti.com SLES126B – DECEMBER 2004 – REVISED MAY 2005 AUDIO SPECIFICATIONS (Single-Ended Output) (continued) PVDD_X = 32 V, GVDD = VDD = 12 V, SE mode, RL = 4 Ω, audio frequency = 1 kHz, AES17 filter, FPWM = 384 kHz, case temperature = 75°C, unless otherwise noted. Audio performance is recorded as a chipset, using TAS5086 PWM processor with an effective modulation index limit of 96.1%. All performance is in accordance with recommended operating conditions unless otherwise specified.
PAGE 10
TAS5142 www.ti.com SLES126B – DECEMBER 2004 – REVISED MAY 2005 ELECTRICAL CHARACTERISTICS RL= 4 Ω, FPWM = 384 kHz, unless otherwise noted. All performance is in accordance with recommended operating conditions unless otherwise specified. PARAMETER TEST CONDITIONS TAS5142 MIN TYP MAX 3 3.3 3.
PAGE 11
TAS5142 www.ti.com SLES126B – DECEMBER 2004 – REVISED MAY 2005 TYPICAL CHARACTERISTICS, BTL CONFIGURATION TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER OUTPUT POWER vs SUPPLY VOLTAGE 120 TC = 75°C PVDD = 32 V One Channel TC = 75°C THD+N @ 10% 110 100 90 PO − Output Power − W THD+N − Total Harmonic Distortion + Noise − % 10 1 6Ω 4Ω 0.1 8Ω 4Ω 80 70 60 6Ω 50 40 30 8Ω 20 10 0 0.01 1 10 0 100 4 8 16 20 24 28 32 G002 G001 Figure 1. Figure 2.
PAGE 12
TAS5142 www.ti.com SLES126B – DECEMBER 2004 – REVISED MAY 2005 TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued) SYSTEM POWER LOSS vs OUTPUT POWER SYSTEM OUTPUT POWER vs CASE TEMPERATURE 40 130 TC = 25°C 110 4Ω 6Ω 100 PO − Output Power − W 30 Power Loss − W 4Ω 120 35 25 6Ω 20 15 10 90 80 70 60 50 8Ω 40 30 5 20 8Ω 10 0 THD+N @ 10% 0 0 20 40 60 80 100 120 140 160 180 200 220 PO − Output Power − W 10 20 30 40 50 G005 Figure 5.
PAGE 13
TAS5142 www.ti.com SLES126B – DECEMBER 2004 – REVISED MAY 2005 TYPICAL CHARACTERISTICS, SE CONFIGURATION OUTPUT POWER vs SUPPLY VOLTAGE 50 10 TC = 75°C Digital Gain = 3 dB TC = 75°C THD+N @ 10% 45 PO − Output Power − W 40 1 3Ω 0.1 35 30 3Ω 25 20 15 4Ω 10 4Ω 5 0.01 1 10 0 50 PO − Output Power − W 0 4 8 12 16 20 24 28 32 PVDD − Supply Voltage − V G008 G009 Figure 8. Figure 9.
PAGE 14
TAS5142 www.ti.com SLES126B – DECEMBER 2004 – REVISED MAY 2005 TYPICAL CHARACTERISTICS, PBTL CONFIGURATION OUTPUT POWER vs SUPPLY VOLTAGE 220 TC = 75°C Digital Gain = 3 dB 10 TC = 75°C THD+N @ 10% 200 180 PO − Output Power − W THD+N − Total Harmonic Distortion + Noise − % TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 1 2Ω 0.1 3Ω 160 2Ω 140 120 100 80 60 3Ω 40 20 0.01 1 10 100 0 200 0 PO − Output Power − W 4 8 12 16 Figure 12.
PAGE 15
TAS5142 www.ti.com SLES126B – DECEMBER 2004 – REVISED MAY 2005 PVDD 10 Ω GVDD 10 µF 3.
PAGE 16
TAS5142 www.ti.com SLES126B – DECEMBER 2004 – REVISED MAY 2005 PVDD 10 Ω GVDD 10 µF 3.
PAGE 17
TAS5142 www.ti.com SLES126B – DECEMBER 2004 – REVISED MAY 2005 10 Ω 100 nF GVDD 10 µF PVDD 47 µF 50 V 10 Ω 3.
PAGE 18
TAS5142 www.ti.com SLES126B – DECEMBER 2004 – REVISED MAY 2005 PVDD 10 Ω GVDD 10 µF 3.
PAGE 19
TAS5142 www.ti.com SLES126B – DECEMBER 2004 – REVISED MAY 2005 PVDD 10 Ω GVDD 10 µF 3.3 Ω 100 nF 47 µF 50 V 10 Ω 1000 µF 50 V 10 nF 50 V TAS5142DKD 100 nF 1 Microcontroller 2 0Ω Optional 3 Shutdown 36 GVDD_B GVDD_A 35 OTW SD 5 VALID 7 OUT_A RESET_AB GND_A PWM_B GND_B OC_ADJ OUT_B PVDD_B 28 AGND BST_B VREG BST_C 10 12 13 M3 26 No connect 16 M2 OUT_C M1 GND_C PWM_C GND_D 10 Ω 100 nF 100 nF 50 V 470 nF 63 V 47 µF 50 V 47 µF 50 V 100 nF 100 V 3.
PAGE 20
TAS5142 www.ti.com SLES126B – DECEMBER 2004 – REVISED MAY 2005 THEORY OF OPERATION POWER SUPPLIES To facilitate system design, the TAS5142 needs only a 12-V supply in addition to the (typical) 32-V power-stage supply. An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog circuitry. Additionally, all circuitry requiring a floating voltage supply, e.g.
PAGE 21
TAS5142 www.ti.com SLES126B – DECEMBER 2004 – REVISED MAY 2005 Characteristics section of this data sheet). Although not specifically required, it is a good practice to hold RESET_AB and RESET_CD low during power down, thus preventing audible artifacts including pops or clicks. temperature has dropped or the supply voltage has increased.
PAGE 22
TAS5142 www.ti.com SLES126B – DECEMBER 2004 – REVISED MAY 2005 • The demodulation-filter inductor must retain at least 5 µH of inductance at twice the OC threshold setting. Unfortunately, most inductors have decreasing inductance with increasing temperature and increasing current (saturation). To some degree, an increase in temperature naturally occurs when operating at high output currents, due to core losses and the dc resistance of the inductor's copper winding.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
PAGE 25
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) TAS5142DDVR HTSSOP DDV 44 2000 330.0 24.4 TAS5142DKDR HSSOP DKD 36 500 330.0 24.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 8.6 15.6 1.8 12.0 24.0 Q1 14.7 16.4 4.0 20.0 24.
PAGE 26
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TAS5142DDVR HTSSOP DDV 44 2000 367.0 367.0 45.0 TAS5142DKDR HSSOP DKD 36 500 337.0 343.0 41.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.