Operating instructions

24
The 2192 sample rate is determined by the Clock and Sample Rate knobs except when the clock
source is set to AES/SPDIF, in which case the sample rate is automatically detected. See Table 4
below.
Clock Knob Setting:
Internal Word 1/2 AES/SPDIF ADAT
Sample Rate
Determined By:
Sample Rate
knob
Sample Rate
knob
Source signal
(automatic)
Sample Rate
knob
Table 4: Clock Source & Sample Rate Interaction
Important: If the clock won’t lock when Clock knob is set to an external source, verify that
the external device is connected to the proper digital input and that it is transmitting a
clock signal. Please note that the 2192 cannot lock to an external device that is set to
slave to the 2192!
Internal
When the Clock knob is set to Internal, the high-quality internal clock of the 2192 is used. At this
setting clock inputs on the rear panel are ignored, and the internal sampling rate is determined by
the Sample Rate knob.
Word 1
When the Clock knob is set to Word 1, the digital clock signal present at the Word 1 BNC clock
input on the rear panel (page 17) is used as the master clock.
At this setting, the Sample Rate knob specifies the multiple or submultiple of the clock rate to be
used internally. For example, if the BNC input is 48kHz, the 44.1 and 48kHz sample rates select
1x sampling, the 88.2 and 96kHz sample rates select 2x sampling, and the 176.4 and 192kHz
sample rates select 4x sampling.
Word 2
When the Clock knob is set to Word 2, the digital clock signal present at the Word 2 BNC clock
input on the rear panel (page 17) is used as the master clock.
At this setting, the Sample Rate knob performs as described above for Word 1.
AES/SPDIF
When the Clock knob is set to AES/SPDIF, the digital clock signal present at the AES/EBU digital
input (page 16) or S/PDIF digital input (page 17) on the rear panel is used as the master clock.
At this setting, the internal sample rate is determined by the digital input alone and the Sample
Rate select knob is ignored.
Important: The clock (AES/EBU or S/PDIF) to be used by the AES/SPDIF Clock knob
setting is determined by the AES/SPDIF switch (page 27).