User Manual

Digital Clocking Primer

Clock jitter affects digital transmission and digital conversion differently, as follows:

• Clock jitter in digital transmission can be caused by a bad source clock, inferior cabling or

improper cable termination, and/or signal-induced noise (called “pattern-jitter” or “symbol-jitter.”)

Digital signal formats like AES/EBU, S/PDIF, and ADAT all embed a clock in the digital signal so the

receiving device can synchronize to the transmitted data bits correctly. The clock used for data

recovery is extracted from the signal using a clock synchronization circuit called a phase-locked-

loop (PLL). This data-recovery PLL must be designed to respond very quickly to attenuate high-

frequency jitter and avoid bit errors during reception. This clock from the data-recovery PLL cannot

be used to generate the clocks used for digital conversion without further clock conditioning! This

is a very common design flaw in most low- and mid-range digital converters.

• Clock jitter in digital conversion is what most people refer to when they discuss jitter. It’s easily

observed in a digital signal by looking at its spectrum in the frequency domain. A jittery signal will

have “side-lobes” around each frequency and/or spurious tones at random, inharmonic

frequencies. Usually, the jitter will be worse with higher signal frequencies. You can test your

converters by sampling a high-quality 10kHz sine wave, and viewing it in the frequency domain

(available with any good wave editing software package).

All modern over-sampling digital converters require a clock (called “m-clock”) that is many times

(typically several MHz) higher than the sample clock. M-clock is easy to generate when the converter is

the clock master, but quite difficult to generate correctly when the converter needs to sync to an

external clock.

External clock typically comes from a dedicated word clock input, or is extracted from the incoming

digital AES/EBU, S/PDIF or ADAT signal. Word clock cannot be used by the converters until it is

multiplied up to the m-clock rate. This requires a PLL or other frequency multiplier circuit which will

either be cheap and jittery, or expensive and clean, depending on who makes the converter. As we said

earlier, the clock recovered from the digital inputs is unsuitable for use as the converter’s m-clock, but

because it’s conveniently at the same frequency, many designers don’t bother cleaning up this signal.

Since the clock recovery, clock multiplier, and clock conditioning circuitry define the jitter for analog

conversion, no external clock source can clean up the jitter introduced by these circuits, regardless of

how perfect the external source clock is. The best they can do is avoid making it any worse, but this is

hardly worth the cost: It’s much better (and less expensive) to get a good converter than it is to try and

fix a bad one with an expensive master clock. The only reason to spend money on a high-quality master

clock is to ensure that multiple devices are synchronized correctly. This is essential for working with

audio for film/video, or when synchronizing multiple high-quality converters. A poor master clock can

also affect imaging and clarity in a multi-track environment.

The 4-710d provides high-quality analog to digital conversion for recording and/or playback. With its

pristine audio path, high-quality clocking, and simple front panel controls, it makes a great master or

slave audio interface for every digital studio, and thus provides a very cost effective way to improve

overall sound quality.

 In order for the 4-710d to detect and lock to a valid external word clock, the frequency of

the incoming word clock must be within ±3% of any of the supported sample rates (44.1,

48, 88.2, 96, 176.4, or 192 kHz). If the frequency of the incoming work clock is not within

±3% of a supported sample rate, the LOCK indicator will glow red, the WORD CLOCK OUT

will be driven at 48 kHz, and the digital outputs will be driven at 48 kHz and muted.