V-color Technology Corp. Memory Module Data Sheet DDR3 R-DIMM Based on 1Gx4 Hynix IC TR316G18D413 Part Number TR316G18D413 Module Type Registered DIMM Memory Type DDR3 Standard JEDEC Pin Number 240 Capacity 16GB Speed 1866 MHz Voltage 1.5V Rank Number 2Rx4 CAS Latency 13 Operation Temperature 0°C ~ +85°C 1 www.v-color.com.
Description V-Color Registered DDR3 SDRAM DIMMs (Registered Double Data Rate Synchronous DRAM Dual In-Line Memory Modules) are low power, high speed operation memory modules that use DDR3 SDRAM devices. These Registered SDRAM DIMMs are intended for use as main memory when installed in systems such as servers and workstations. FEATURES Power Supply: VDD=1.5V (1.425V to 1.575V) VDDQ = 1.5V (1.425V to 1.575V) VDDSPD=3.0V to 3.6V VDDQ = 1.5V (1.425V to 1.575V) VDDSPD=3.0V to 3.
Pin Assignments Pin # Front Side (left 1–60) 1 VREFDQ 121 2 VSS 3 DQ0 4 5 6 Back Side Pin # (right 121 –180) Pin # 61 122 DQ4 123 DQ5 DQ1 124 VSS VSS 125 DQS0 126 TDQS9 NC,DQS9, Pin # (left 61–120) VSS DM0,DQS9, Front Side Back Side (right 181–240) A2 181 A1 62 VDD 182 VDD 63 NC, CK1 183 VDD 64 NC, CK1 184 CK0 65 VDD 185 CK0 66 VDD 186 VDD 67 VREFCA 187 EVENT, NC DQS0 127 TDQS9 VSS 8 VSS 128 DQ6 68 Par_In, NC 188 A0 9 DQ2 129 DQ7 69
Pin # Front Side Back Side Pin # Pin # (right 121 –180) (left 1–60) 32 VSS 152 33 DQS3 153 34 DQS3 154 35 VSS 36 DM3,DQS12, Front Side Pin # (left 61–120) Back Side (right 181–240) DM5,DQS14, 92 VSS 212 93 DQS5 213 TDQS12 VSS 94 DQS5 214 TDQS14 VSS 155 DQ30 95 VSS 215 DQ46 DQ26 156 DQ31 96 DQ42 216 DQ47 37 DQ27 157 VSS 97 DQ43 217 VSS 38 VSS 158 CB4, NC 98 VSS 218 DQ52 39 CB0, NC 159 CB5, NC 99 DQ48 219 DQ53 40 CB1, NC 160 VSS 100 D
Pin Descriptions Pin Name Description Num Pin Name Description ber 1 ODT[1:0] On Die Termination Inputs Clock Input, negative line 1 DQ[63:0] Data Input/Output CK1 Clock Input, positive line 1 CB[7:0] CK1 Clock Input, negative line 1 DQS[8:0] Clock Enables 2 DQS[8:0] Row Address Strobe 1 CK0 Clock Input, positive line CK0 CKE[1:0] DM[8:0]/ RAS Data check bits Input/Output Data strobes Num ber 2 64 8 9 Data strobes, negative line 9 Data Masks / Data strobes, 9 DQS[17:9],
Absolute Maximum Ratings Symbol VDD VDDQ Parameter Rating Units Notes Voltage on VDD pin relative to Vss - 0.4 V ~ 1.80 V V 1,3 Voltage on VDDQ pin relative to Vss - 0.4 V ~ 1.80 V V 1,3 - 0.4 V ~ 1.80 V V 1 -55 to +100 °C 1, 2 VIN, VOUT Voltage on any pin relative to Vss TSTG Storage Temperature Notes: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
Standard Speed Bins DDR3-800 Speed Bins and Operations Speed Bin DDR3-800E CL - nRCD - nRP 6 -6 -6 Unit Parameter Symbol min max Internal read command to first data tAA 15 20 ns ACT to internal read or write delay time tRCD 15 — ns PRE command period tRP 15 — ns ACT to ACT or REF command period tRC 52.5 — ns ACT to PRE command period tRAS 37.5 9 * tREFI ns tCK(AVG) 2.5 3.
DDR3-1066 Speed Bins and Operations Speed Bin DDR3-1066F CL - nRCD - nRP 7 -7-7 Parameter Unit Note Symbol min max tAA 13.125 20 ns tRCD 13.125 — ns tRP 13.125 — ns tRC 50.625 — ns tRAS 37.5 9 * tREFI ns CWL = 5 tCK(AVG) 2.5 3.
DDR3-1333 Speed Bins and Operations Speed Bin DDR3-1333H CL - nRCD - nRP 9 -9-9 Parameter Internal read Symbol tAA command to first data ACT to internal read or ACT to ACT or REF tRCD tRP tRC command period ACT to PRE command min Note max 13.5 20 ns — ns — ns — ns (13.125) 5,10 write delay time PRE command period Unit 13.5 (13.125) 5,10 13.5 (13.125) 5,10 49.5 (49.125) 5,10 tRAS 36 9 * tREFI ns CWL = 5 tCK(AVG) 2.5 3.
DDR3-1600 Speed Bins and Operations Speed Bin DDR3-1600K CL - nRCD - nRP 11 - 11 -11 Parameter Internal read Symbol tAA command to first data ACT to internal read or min Note max 13.75 20 ns — ns — ns — ns (13.125) 5,10 tRCD write delay time PRE command period Unit 13.75 (13.125) 5,10 tRP 13.75 (13.125) 5,10 ACT to ACT or REF tRC command period ACT to PRE command 48.75 (48.125) 5,10 tRAS 35 9 * tREFI ns CWL = 5 tCK(AVG) 2.5 3.
DDR3-1866 Speed Bins and Operations Speed Bin DDR3-1866M CL - nRCD - nRP 1 3 - 1 3 -1 3 Parameter Symbol Internal read command tAA to first data ACT to internal read or tRCD write delay time min 13.91 Note max 20 ns — ns — ns 9 * tREFI ns - ns 3.3 ns 1,2,3,9 (13.125) 5,11 13.91 (13.125) 5,11 PRE command period ACT to PRE command Unit tRP tRAS 13.91 (13.125) 5,11 34 period ACT to ACT or PRE tRC command period CL = 6 CL = 7 CL = 8 CL = 9 CL = 10 CL = 11 47.91 (47.
Speed Bin Table Notes Absolute Specification (TOPER; VDDQ = VDD = 1.5V +/- 0.075 V); 1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When mak ing a selection of tCK(AVG), both need to be fulfilled: Requirements from CL setting as well as require ments from CWL setting. 2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL all possible intermediate frequencies may not be guaranteed.
10. DDR3 SDRAM devices supporting optional down binning to CL=7 and CL=9, and tAA/tRCD/tRP must be 13.125 ns or lower. SPD settings must be programmed to match. For example, DDR3-1333H devices supporting down binning to DDR3-1066F should program 13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin (Byte 18), and tRPmin (Byte 20). DDR3-1600K devices supporting down binning to DDR31333H or DDR3-1600F should program 13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin (Byte 18), and tRPmin (Byte 20).
Timings used for IDD, IPP and IDDQ Measurement DDR3-1333 DDR3-1600 DDR3-1866 7 -7 -7 9 -9-9 11 - 11 -11 1 3 - 1 3 -1 3 1.875 1.5 1.25 1.
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