DEC 3000 300/400/500/600/700 /800/900 AXP Models System Programmer’s Manual Order Number: EK–D3SYS–PM. B01 This manual describes the behavior of DEC 3000 AXP architecture as it pertains to writing system-level software, such as operating systems and drivers. This manual describes the behavior of 300, 300L, 300X, 300LX, 400, 400S, 500, 500S, 500X, 600, 600S, 700, 800, 800S, and 900 models. Revision/Update Information: This is a revised manual.
First Printing, September 1993 Revised, July 1994 Digital Equipment Corporation makes no representations that the use of its products in the manner described in this publication will not infringe on existing or future patent rights, nor do the descriptions contained in this publication imply the granting of licenses to make, use, or sell equipment or software in accordance with the description.
Contents Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii 1 Introduction to the DEC 3000 Models 300/400/500/600/700/800/900 AXP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 1–6 1–9 1–13 1–16 1–19 Memory Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Address Spaces . . . . . . . . . . . .
3.3.9 TURBOchannel Reset Register (TCRESET)—1.C2A0.0000 . . . . . . . . . 3–19 4 Address ASIC Registers (400/500/600/700/800/900 Models) 4.1 4.1.1 4.1.2 4.1.3 4.1.4 4.2 4.2.1 4.2.2 4.2.3 Memory Configuration Registers . . . . . . . . . . . . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boot Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Improper Configuration . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.3 7.3.4 7.3.5 7.3.6 7.3.7 7.3.8 7.3.9 7.3.10 7.3.11 7.3.12 7.3.13 7.3.14 7.3.15 7.3.16 7.3.17 7.3.18 7.3.19 7.4 7.5 7.6 7.7 7.8 7.8.1 7.8.2 Communication Port 1 Receive DMA Pointer—1.A004.0040/1.E004.0040 . . . . . . . . . . . . . . . . . . . . . . . Printer Port Transmit DMA Pointer—NA/ 1.E004.0050 . . . . . . . Printer Port Receive DMA Pointer—NA/1.E004.0060 . . . . . . . . ISDN Transmit DMA Pointer—1.A004.0080/1.E004.0080 . . . . . ISDN Transmit DMA Buffer Pointer—1.A004.0090/1.E004.
DMA Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA Arbitration (300 Models) . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA Arbitration (400/500/600/700/800/900 Models) . . . . . . . . . . I/O Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Conflicts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Masked I/O Read Operations . . . . . . . . . . . . . . . . . .
11 CPU Power Up and Initialization 11.1 Processor initialization . . . . . . 11.1.1 Power-On Reset Sequence 11.1.2 SROM Sequence . . . . . . . . 11.1.3 SYSROM Sequence . . . . . 11.2 Bcache Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.4.3 DEPOSIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.4.4 EXAMINE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.4.5 HALT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.4.6 HELP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.4.7 INITIALIZE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.4.8 LOGIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.4.9 REPEAT . . . . . . . . . . . . . . . .
18 TURBOchannel Support 19 Nonvolatile RAM 19.1 19.2 19.3 19.4 19.5 19.6 19.7 19.8 19.9 19.10 19.11 19.12 19.13 NVR Console Mailbox Register . . . . . . . . . . . . . . . . . . NVR Console Flags Register (CPFLG) . . . . . . . . . . . . . NVR Keyboard Type Register . . . . . . . . . . . . . . . . . . . . NVR Console Device Type Register . . . . . . . . . . . . . . . Temporary Storage (TEMP) . . . . . . . . . . . . . . . . . . . . . NVR Battery Check Data (BAT_CHK) . . . . . . . . . . . . .
Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 x DEC 3000 AXP 300 Models: Functional Block Diagram . . . . . DEC 3000 AXP 400 Models: Functional Block Diagram . . . . . DEC 3000 AXP 500 Models: Functional Block Diagram . . . . . DEC 3000 AXP 600/700 Models: Functional Block Diagram . . DEC 3000 AXP 800/900 Models: Functional Block Diagram . . ABOX_CTL Register: 300 Models . . . . . . . . . . . . . . . . . . . . . .
46 47 48 Dense I/O Space Addressing: 300 Models . . . . . . . . . . . . . . . . . . . . . . Sparse I/O Space Addressing: 400/500/600/700/800/900 Models . . . . . . Sparse I/O Space Addressing: 300 Models . . . . . . . . . . . . . . . . . . . . . . A–2 A–3 A–3 Conventions Used in this Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit Name Conventions Used in this Guide . . . . . . . . . . . . . . . . . . . . . System Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 59 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 xii CPU State Before SCB Routines . . . . . . . . . . . . . . . . . . . . . Dual SCSI Error/Interrupt Matrix . . . . . . . . . . . . . . . . . . . . Error Insertion Techniques . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Pin Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Preface The DEC 3000 300/400/500/600/700/800/900 AXP Models are a family of highperformance deskside and desktop workstations that use Digital’s DECchip 21064 RISC-style microprocessor. They comprise a family of systems based on the Digital Alpha AXP architecture, providing a 64-bit computing environment. Intended Audience This manual is intended for design engineers and programmers who write such system-level software as operating systems and drivers.
• Chapter 9 describes programming considerations and restrictions for I/O transactions—I/O read and write restrictions, DMA, interrupt handling during I/O operations, TURBOchannel usage (system-specific), JUNKIO subsystem, and the dual SCSI interface.
• DEC 3000 Model 400 AXP Workstation Documentation Kit (EK–SNDPR–DK) • DEC 3000 Model 400/400S AXP Server Documentation Kit (EK–SNPSV–DK) • DEC 3000 Model 500/500S AXP Server Documentation Kit (EK–FLAMI–DK) • DEC 3000 Model 500/500S AXP Workstation Kit (EK–FLMNG–DK) • DEC 3000 Model 500X AXP Documentation Kit (EK–D5AXP–DK) • DEC 3000 Model 600/600S/700 AXP Information Kit (EK–SNDWS–DK) • DEC 3000 Model 800/800S/900 AXP Information Kit (EK–FLMWS–DK) • NCR 53C94-95-96 Advanced SCSI Controller (
Table 2 lists the conventions for naming bits: Table 2 Bit Name Conventions Used in this Guide xvi Convention Description 0 Describes a bit that is ignored on write operations and is read as 0. 1 Describes a bit that is ignored on write operations and is read as 1. R/W Read/write. A bit or field that may be read or written by software. RO A read-only bit that can be read by software. It is written by hardware. Software writes are ignored. WO Write-only.
1 Introduction to the DEC 3000 Models 300/400/500/600/700/800/900 AXP The DEC 3000 Models 300/400/500/600/700/800/900 AXP is a family of desktop and deskside workstations that support the DECchip 21064–AA CPU implementation of the Alpha AXP architecture. These models’ I/O system is TURBOchannel-based and has embedded I/O devices. This chapter briefly describes the components and functions of each model and covers the following topics: • System description: 300 models (Section 1.
1.1 System Description: 300 Models Figure 1 is a functional block diagram of the DEC 3000 AXP 300 models. Numbers along communication lines indicate their bus width. Major system components are: • CPU: A DECchip 21064–AA CPU, including on-chip 8 KB instruction and 8 KB data caches, and a 64 KB (8 KB) serial boot ROM. Section 2.5 discusses CPU registers that must be assigned specific values at startup. • Cache: A module-level write-back backup cache, or Bcache. The Bcache contains 256 KB, 32-byte blocks.
Figure 1 DEC 3000 AXP 300 Models: Functional Block Diagram Clock Serial ROM 21064 Data 64 Address 28 Cache (256KB) Buffer Buffer Memory SIMMs 16-256MB Memory, CPU TURBOchannel Control Logic Data 64 Buffer Graphics: -SFB -2MB VRAMS -RAMDAC -etc I/O Subsystem: -Core I/O ASIC -Ethernet -ISDN -Serial -ROMs -Audio -LEDs Buffer (Except 300L) Buffer 2 TURBOchannel Option Slots TURBOchannel 32 SCSI TCDS N/C MLO-012116 Introduction to the DEC 3000 Models 300/400/500/600/700/800/900 AXP 1–3
• TURBOchannel Option Slots: The 300, 300X, and 300LX models contain two TURBOchannel option slots. Each slot has 64 MB of I/O address space. The 300L model contains no option slots. • I/O Subsystem: An interface called the JUNKIO subsystem, which is connected to the TURBOchannel. The IOCTL ASIC implements this interface. Chapter 7 describes IOCTL ASIC control of the subsystem and Section 9.
• SCSI Interface: A TURBOchannel dual SCSI interface chip (TCDS) is connected to the TURBOchannel bus, but only one NCR53C94 SCSI controller chip interfaces to the TCDS ASIC and provides a single-ended, 8-bit, 5 MB/s SCSI port. This port drives one SCSI drop inside the system box and is also available outside the box for further expansion. Chapter 8 discusses the TURBOchannel Dual SCSI ASIC. Hardware Jumpers Table 3 lists system jumpers, their possible position, and the correspoding function.
1.2 System Description: 400 Models Figure 2 is a functional block diagram of the DEC 3000 AXP 400 models.
System components are: • CPU: A DECchip 21064–AA CPU, including on-chip 8-KB instruction and 8-KB data caches, and a 64-KB serial boot ROM. A 64-KB stream holds the primitive boot code for booting the operating system. Jumpers provide for the selection of up to seven other streams for diagnostic and other purposes. (The entire UVPROM is 64 K x 8.) Section 2.5 discusses CPU registers that must be assigned specific values at startup.
• JUNKIO Interface: An interface called the JUNKIO subsystem, which is connected to the TURBOchannel. The IOCTL ASIC implements this interface. Chapter 7 describes IOCTL ASIC control of the subsystem and Section 9.5 discusses programming the subsystem, which provides: A nonvolatile time-of-year clock based on the Dallas Semiconductor DS 1287A Real-Time Clock (RTC) Four serial lines, through two Zilog SCC (Z85C30) dual UARTS (universal asynchronous receiver/transmitters)—SCC0 and SCC1.
1.3 System Description: 500 Models Figure 3 is a functional block diagram of the DEC 3000 AXP 500 models.
System components are: • CPU: A DECchip 21064–AA CPU, including on-chip 8-KB instruction and 8-KB data caches, and a 64-KB serial boot ROM. A 64-KB stream holds the primitive boot code for booting the operating system. Jumpers provide for the selection of up to seven other streams for diagnostic and other purposes. (The entire UVPROM is 64 K x 8.) Section 2.5 discusses CPU registers must be assigned specific values at startup.
• JUNKIO Interface: An interface called the JUNKIO subsystem, which is connected to the TURBOchannel. The IOCTL ASIC implements this interface. Chapter 7 describes IOCTL ASIC control of the subsystem and Section 9.
• Graphics Subsystem An 8-plane color graphics subsystem, called the CXTurbo, which is connected to the TURBOchannel. The CXTurbo has 256 KB of writable console ROM and supports an 8-plane color monitor in the resolution/refresh rate combinations of: * 1280 x 1024 @ 72 Hz * 1280 x 1024 @ 66 Hz The refresh rate is switch-selectable. Chapter 6 describes the CXTurbo graphics subsystem. • SCSI Interface: A dual SCSI interface chip (TCDS), which is connected to the TURBOchannel.
1.4 System Description: 600/700 Models Figure 4 is a functional block diagram of the DEC 3000 AXP 600/700 models.
System components are: • CPU: A DECchip 21064–AA CPU, including on-chip 8-KB instruction and 8-KB data caches, and a 64-KB serial boot ROM. A 64-KB stream holds the primitive boot code for booting the operating system. Jumpers provide for the selection of up to seven other streams for diagnostic and other purposes. (The entire UVPROM is 64 K x 8.) Section 2.5 discusses CPU registers that must be assigned specific values at startup.
• JUNKIO Interface: An interface called the JUNKIO subsystem, which is connected to the TURBOchannel. The IOCTL ASIC implements this interface. Chapter 7 describes IOCTL ASIC control of the subsystem and Section 9.
1.5 System Description: 800/900 Models Figure 5 is a functional block diagram of the DEC 3000 AXP 800/900 models.
System components are: • CPU: A DECchip 21064–AA CPU, including on-chip 8-KB instruction and 8-KB data caches, and a 64-KB serial boot ROM. A 64-KB stream holds the primitive boot code for booting the operating system. Jumpers provide for the selection of up to seven other streams for diagnostic and other purposes. (The entire UVPROM is 64 K x 8.) Section 2.5 discusses CPU registers must be assigned specific values at startup.
• JUNKIO Interface: An interface called the JUNKIO subsystem, which is connected to the TURBOchannel. The IOCTL ASIC implements this interface. Chapter 7 describes IOCTL ASIC control of the subsystem and Section 9.
1.6 CPU Differences Among Models The next table lists CPU differences. Other differences are listed in discussions of specific subsystems and programming requirements. Model Clock Rate Cache Loop Bus Width Bandwidth Time 300 150 MHz 26.66 ns 64 bits read = 300 MB/s write = 240 MB/s 300L 100 MHz 40.00 ns 64 bits 175 MHz 28.50 ns 64 bits 125 MHz 32.
2 Memory and I/O Addressing This chapter describes the DEC 3000 AXP systems’ address maps, the methods of addressing I/O space, and system I/O registers. Note The addresses are 34-bit physical addresses, numbered in hexadecimal notation. In all register diagrams, an X in a bit position indicates that the contents of the bit are ignored when written. This chapter covers the following topics: • Memory alignment (Section 2.1) • Memory address spaces (Section 2.2) • I/O address spaces (Section 2.
2.1 Memory Alignment All CPU accesses to memory have a minimum size of 32 bytes or 4 quadwords. The 32 bytes are on a naturally aligned boundary. A TURBOchannel DMA access of main memory can start on any naturally aligned longword boundary. A DMA operation can be as short as one longword but cannot exceed 128 longwords. DMA operations on data greater than 128 longwords can be performed, provided that the requesting DMA device drop its request and rearbitrate for the TURBOchannel every 128 longwords. 2.
2.3 I/O Address Spaces You use Load and Store memory instructions to map and access I/O space. Note Accessing nonexistent memory locations and nonexistent I/O registers in the TURBOchannel address space yield UNPREDICTABLE results. Accessing a non-existent I/O device on TURBOchannel causes the bus timeout. The 4 GB of I/O space is divided into 8 512-MB slots corresponding to I/O ports. • Address bits <31:29> select a slot. • Slots are further divided into dense and sparse space.
Table 6 300 Model I/O Address Map Slot Number Start Address End Address Size Device Space 0 1.0000.0000 1.03FF.FFFF 64 MB TC option number 0 Dense 1.0400.0000 1.0FFF.FFFF 192 MB TC option number 0 Reserved 1.1000.0000 1.17FF.FFFF 128 MB TC option number 0 Sparse 1.1800.0000 1.1FFF.FFFF 128 MB TC option number 0 Reserved 1.2000.0000 1.23FF.FFFF 64 MB TC option number 1 Dense 1.2400.FFFF 1.2FFF.FFFF 192 MB TC option number 1 Reserved 1.3000.0000 1.37FF.
Table 7 400/500/600/700/800/900 Models I/O Address Map Slot Number Start Address End Address Size Device Space 0 1.0000.0000 1.01FF.FFFF 32 MB TC option number 0 Dense (500 models only) 0 1.0200.0000 1.0FFF.FFFF 224 MB Reserved 0 1.1000.0000 1.13FF.FFFF 64 MB TC option number 0 0 1.1400.0000 1.1FFF.FFFF 192 MB Reserved 1 1.2000.0000 1.21FF.FFFF 32 MB TC option number 1 1 1.2200.0000 1.2FFF.FFFF 224 MB Reserved 1 1.3000.0000 1.33FF.FFFF 64 MB TC option number 1 1 1.
Table 7 (Cont.) 400/500/600/700/800/900 Models I/O Address Map Slot Number Start Address End Address Size Device 4 1.8200.0000 1.8FFF.FFFF 224 MB Reserved 4 1.9000.0000 1.93FF.FFFF 64 MB TC option number 4 (500/800/900 models); TC option number 1 (400/600/700 models) 4 1.9400.0000 1.9FFF.FFFF 192 MB Reserved 5 1.A000.0000 1.A1FF.FFFF 32 MB TC option number 5 (500/800/900 models); TC option number 2 (400/600/700 models) 5 1.A200.0000 1.AFFF.FFFF 224 MB Reserved 5 1.B000.0000 1.
2.4 TURBOchannel Interface Bit Decode Map for I/O Addresses An I/O address takes on three forms in the system:1 1. Software-generated (by the macroinstruction) 2. CPU chip-logic-generated (to the system module) 3. TURBOchannel-interface generated (on the TURBOchannel) The following bit decode lists describe physical addresses generated by the CPU.
300 Model Bit Decode List • I/O and memory space split 33 32 0 0 1 1 − − − − 0 1 0 1 Main Memory TURBOchannel I/O Space Diagnostics Only Diagnostics Only MR−0057−93RAGS • Bit decode map for TURBOchannel I/O space 29 31 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 − − − − − − − − Option #0 Option #1 Unused Unused SCSI Interface IOCTL ASIC and JUNKIO CXTurbo Interface System CSRs MR−0058−93RAGS • Dense vs.
2.5 CPU Registers This section discusses: • ABOX control register (Section 2.5.1) • The bus interface unit control register (Section 2.5.2) Both registers must be assigned specific values at startup time, as shown in the corresponding bit diagrams. Many values must be maintained during operation. The required values of the registers whose contents affect system hardware are outlined in this section.1 PALcode initializes them during initial system startup, unless otherwise noted. 2.5.
Figure 7 ABOX_CTL Register: 400/500/600/700/800/900 Models 11 10 09 08 07 06 05 04 03 02 01 00 0 1 1 DC_EN DC_FHIT 1 1 0 WB_DIS MCHK_EN CRD_EN IC_SBUF_EN MR−0061−93RAGS The ABOX_CTL fields have the following meanings when programmed as above. Position Field Function 0 WB_DIS Clear. CPU write buffer enabled to write. 1 MCHK_EN Set. Machine checks are enabled. 2 CRD_EN Set. Correctable ECC errors cause interrupts. 3 IC_SBUF_EN Clear in 300 models. Icache stream buffer is disabled.
2.5.2 Bus Interface Unit Control Register (BIU_CTL) The BIU_CTL register is internal to the DECchip 21064 CPU. Only 36 bits of this 64-bit control register are used during normal system operation. 300 model register bit settings differ from 400/500/600/700/800/900 register bit settings.
Position Field Function 31 BAD_TCP Bad tag control parity. 35:32 BC_PA_DIS 4-bit field. Set. Only physical addresses with A<33:32> = 00 can be cached. 36 BAD_DP Bad data parity. Note The 300 model has a faster read/write access to its Bcache than other models, because the 300 model drives only half as many Bcache RAMs. 2.6 Bcache Tag Space The Bcache is the system module-level secondary cache. From physical address 0.8000.0000 to address 0.FFFF.
3 TURBOchannel I/O Registers This chapter covers the following topics: • I/O interface register map (300 models) (Section 3.1) • I/O control and status registers (300 models) (Section 3.2) • TURBOchannel interface registers (400/500/600/700/800/900 models) (Section 3.3) Note In all register diagrams, an X in a bit position indicates that the contents of the bit are ignored when written. All addresses are dense space addresses, except where dense and sparse space do not map to the same register.
3.2 I/O Control and Status Registers (300 Models) All CSRs are quadword-aligned but use only the first longword of the quadword. Note The status of unused bits in the CSRs is UNDEFINED and must be masked out by software. Table 9 lists TURBOchannel control and status registers: Table 9 TURBOchannel Control and Status Registers (300 Models) Start Address End Address Size Register Access Discussed In 1.E000.0000 1.E000.0003 4B Interrupt register R Section 3.2.1 1.E000.0004 1.E000.
3.2.1 Interrupt Register (IR)—1.E000.0000 The interrupt register holds the interrupt reasons for machine check interrupts and I/O interrupts. Its bits are clear on initialization. The register’s format and contents are: 31 30 29 28 27 26 05 04 03 02 01 00 I S S U U O C F U U I I I T T B M B C C C P P T O T MR−0065−93RAGS Bit Access Description 0 NA Unused 1 NA Unused 2 R Smart frame buffer (SFB) Interrupt. Sets when the SFB applicationsspecific integrated circuit (SFB ASIC) interrupts.
3.2.2 TURBOchannel Control and Status Register (TCSR)—1.E000.0008 The TURBOchannel control and status register (TCSR) indicates which TURBOchannel option was involved in a failing transaction. The register’s format and contents are: 31 05 04 03 02 01 00 T T T T T C C C C C 4 3 2 1 0 MR−0066−93RAGS Bit Access Name Description 0 R TC active port[0] When set along with an error bit in IR, indicates that TC Option 0 was involved in the failing transaction.
3.2.3 Memory Configuration Register (MCR)—1.E000.0010 The following sections discusss: • MCR use and format (Section 3.2.3.1) • Memory configuring using the MCR (Section 3.2.3.2) 3.2.3.1 MCR Use and Format This register specifies memory SIMM sizes. It is accessible by the console and by the operating system through both I/O read and write operations. The register’s format and contents are: 31 04 03 02 01 00 S S S S P P P P 3 2 1 0 XXXXX MR−0067−93RAGS Bit Access Description 0 R SIMMPAIR0 SIZE.
To configure memory, perform the following: 1. Read the MCR to determine sizes of memory SIMMPairs. Each bit in the MCR shows whether a SIMMPair is 16 or 64 MB.1 (See Section 3.2.3.) 2. Read the MCR to find out the possible maximum address of contiguous memory. For example, if MCR<3:0> = 1111, the maximum amount of contiguous memory is 256 MB; if MCR<3:0> = 0011, the maximum amount of contiguous memory is no greater then 160 MB but could be as low as 128 MB. (See Section 3.2.3.
3.2.4 Diagnostic LED Register (LED)—1.E000.0018 These bits turn LEDs on and off. The register’s format and contents are: 31 24 23 22 21 20 19 18 17 16 15 UU L E D 7 L E D 6 L E D 5 L E D 4 L E D 3 L E D 2 L E D 1 L E D 0 00 UU MR−0068−93RAGS Bit Access Name Description 15:0 - Unused UNDEFINED 23:16 W LED[7:0] When set, LED is off. When clear, LED is on. (Bits are cleared on power-up reset.
3.3 TURBOchannel Interface Registers (400/500/600/700/800/900 Models) All CSRs are quadword-aligned but use only the first longword of the quadword. Note The status of unused bits in the CSRs is UNDEFINED and must be masked out by software. All addresses are dense space addresses, except where dense and sparse space do not map to the same register. To generate the sparse space equivalents of dense pace addresses, set bit [28] and shift bits [27:2] left by one, dropping any overflow bits.
Table 10 (Cont.) TURBOchannel Control and Status Registers (400/500/600/700 /800/900) Models Start Address End Address Size Register Access Discussed In Dense space 1.C280.0000 1.C281.FFFF 128 KB Scatter/gather map1 R Chapter 5 1.C280.0000 1.C281.FFFF 128 KB Interrupt mask register1 W Section 3.3.6 1.C281.FFFC 1.C281.FFFF 4 B Interrupt mask register (by convention)1 W Section 3.3.6 1.C282.0000 Reserved W Section 3.3.9 R Section 3.3.7 RC Section 3.3.7 R/W Chapter 5 1.C3FF.
3.3.1 I/O Slot Configuration (IOSLOT) Register—1.C200.0000, 1.C200.0020 (Alternate address) The I/O slot configuration register sets up the characteristics of each TURBOchannel slot, whether built-in or option. Each 3-bit register field corresponds to one slot and contains PBS bits. During initialization, these bits are set to the default 0 for each slot.
Bits Access Init.
3.3.2 TURBOchannel Configuration (TCCONFIG) Register—1.C200.0008 The TURBOchannel ASIC configuration register indicates the page size and the DMA buffer threshold number. The TCCONFIG register should be written only by powerup code in the console ROM. It consists of two fields: • Bit 8 is the page-size field, specifying 8-KB or 512-byte pages to the hardware.
3.3.3 Failing Address Register (FADR)—1.C200.0010 The FADR is the failing address register for DMA and I/O transactions. It holds the starting longword address of a DMA transaction or the quadword address for an I/O transaction when a TURBOchannel parity error or ECC error occurs. The address is the address located on the TURBOchannel address lines, It is is a longword address, virtual if the scatter/gather map was used to perform the operation.
3.3.4 TURBOchannel Error Register (TCEREG)—1.C200.0018 The TURBOchannel ASIC error register saves useful state during error conditions. It locks on the first error (loads data) and unlocks on any write. Write operations to this register or the FADR register unlock both. Note Writing to this register unlocks both TCEREG and FADR. While unlocked, the contents of this register are UNPREDICTABLE.
3.3.5 Memory Configuration Registers Memory configuration registers are described in Section 4.1. 3.3.6 Interrupt Mask Register (IMR)—1.C240.0000 The interrupt mask register holds copies of the reasons for machine check interrupts and the mask for I/O interrupts. Note Reading dense space 1.C240.0000 reads the interrupt mask register. Reading the corresponding sparse space 1.D480.0000 reads the interrupt register. Reading the interrupt mask register at address 1.C260.0000 clears the interrupt register.
Bits Access Init. Description 31 R 0 Scatter/gather parity error Table 11 IMR—1.C281.FFFC Bits Access Init. Description 5:0 W 0 TURBOchannel interrupt mask for the option slots (0=Enable, 1=Disable) 31:6 W IGNORED Writing the Interrupt Mask Register The interrupt mask register can be written using any of the dense space scatter/gather map addresses. By convention, use the address given in Table 11, 1.C281.FFFC.
3.3.7 Interrupt Register (IR)—1.D480.0000 The interrupt register holds the interrupt reasons for machine check interrupts and I/O interrupts. Note Reading dense space 1.C240.0000 reads the interrupt mask register. Reading the corresponding sparse space 1.D480.0000 reads the interrupt register. The register’s format and contents are: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 D S T T T X D S P N I T T B B E P C 2 B E E V A L O E E R E R K F O 09 08 UU 00 TC INT<8:0> MR−0074−93RAGS Bits Access Init.
Table 12 IR—1.D4C0.0000 Bits Access Init.
3.3.8 Scatter/Gather Map Scatter/gather registers are described in Chapter 5. 3.3.9 TURBOchannel Reset Register (TCRESET)—1.C2A0.0000 Any I/O write operation to the TURBOchannel reset register causes a full TURBOchannel reset cycle of 250 ms duration. An attempt to access TURBOchannel I/O space during this time causes the transaction to be delayed until the reset operation is completed. This reset affects only the TURBOchannel slots (including CoreIO, SCSI, and CXTurbo).
4 Address ASIC Registers (400/500/600/700/800/900 Models) In 400/500/600/700/800/900 models, the address ASIC controls access to two regions of I/O space: the region used to read from and write to the memory configuration registers and the region used either to write to the victim address counter register or to read the victim address register.1 This chapter covers the following topics: • Memory configuration registers (Section 4.1) • VAR/VACR victim address register and counter register (Section 4.
4.1 Memory Configuration Registers Memory configuration registers (1.C220.0000-1.C227.FFFF) are used to specify memory SIMM sizes and control which bank of RAMs is accessed on a memory read or write operation. The registers are accessible by the console and by the operating system through both I/O read and write operations. The console must determine the size of each bank and write the correct information to the MCRs at boot time.
Note Bits below <23> and above <29> need never be compared: the smallest bank is 8 MB and the 500/500S/800/900 models are limited to 1 GB maximum memory. • Mask half (address bits <26:23> The bank size determines the mask bit: Bank Size Mask<26:23> 8 MB 0000 32 MB 0011 128 MB 1111 4.1.2 Boot Time At boot time, the console must assume that all banks are of the largest possible size (128 MB).
Once the console has ascertained the size of each bank, it writes the correct values into the MCRs.
The address for a read operation from an MCR is: 33 32 31 0 20 19 18 C22 1 0 16 15 00 MCR# XXXXX MR−0075−93RAGS Bit fields have the following meanings: Bit Field Contents 4:0 Ignored on write operations 15:5 Ignored on read operations; on write operations: Bit Field Contents 8:5 Mask (<26:23>) bits on the data bus are ignored; the data is in the address bits.
4.2 Victim Address Register and Counter Register (VAR/VACR) The operating system can use the victim address register (VAR) and victim address counter register (VACR) to identify blocks in the cache that are thrashing. Those blocks can be remapped to reduce the thrashing and improve cache performance. The VAR captures every nth Bcache Victim Address.
The data returned by a read operation from a VAR is: 31 21 20 UNPREDICTABLE 05 04 VAR<20:5> 00 UNP MR−0078−93RAGS Address ASIC Registers (400/500/600/700/800/900 Models) 4–7
5 Scatter/Gather (Virtual DMA) RAMs (400/500/600/700/800/900 Models) Scatter/gather registers in the DEC 3000 (400/500/600/700/800/900 models) carry out an address translation scheme to implement virtual DMA.1 This chapter covers the following topics: • Scatter/gather register map (Section 5.1) • Organization (Section 5.2) • Writing and reading scatter/gather map entries (Section 5.3) 5.
5.2 Organization Each entry’s format and contents are: 23 22 21 20 04 03 V F P PPN 00 UNP MR−0079−93RAGS Bits Description 3:0 UNPREDICTABLE. Unused and ignored in the parity calculation. 20:4 Physical page number. Translation of the virtual index: 17 bits. 21 Parity bit. Odd parity bit for the entire entry. 22 Funny bit. When set to 1, forces bad parity into the scatter/gather map for diagnostic purposes. 23 Valid bit.
Note The scatter/gather map acts on a DMA read or write operation, only if the scatter/gather bit is set for that device in the TURBOchannel interface’s IOSLOT register (see Section 3.3.1). 5.3 Writing and Reading Scatter/Gather Map Entries Software must not write to a map entry while DMA is in progress through that entry.
6 CXTurbo Graphics Subsystem: 300/500 Models The 300 and 500 models feature the CXTurbo graphics subsystem, although small differences exist between the 300 model and 500 model CXTurbo. The CXTurbo graphics subsystem provides 8-plane graphics with enhanced hardware features common to graphics accelerators. The graphics subsystem nonetheless remains a TURBOchannel subsystem with one ASIC for hardware control.
6.1 Comparison of Features The 300 models feature the same CXTurbo hardware as the 500 models, with these exceptions: 300 Models 500 Models Support 1 video oscillator: 1280x1024 @ 72 Hz—300, 300X, 300LX models; 1024x768 @ 72 Hz—300L model. Support only dense space access of CXTurbo I/O registers and frame buffer. Support 2 video oscillators: 1280x1024 @ 66 Hz or 72 Hz (user selectable). Do not support byte write operations to CXTurbo. Support byte write operations to CXTurbo.
6.2 CXTurbo Address Map The CXTurbo has 16 MB of available I/O address space. However, only 4 MB is used to implement the 8-plane graphics system. Table 14 lists the CXTurbo address map for 300 and 500 models Table 14 CXTurbo Address Map Start Address End Address Size Description Discussed In 300 Models 1.C200.0000 1.C20F.FFFF 1 MB Reserved, system FEPROM 1.C210.0000 1.C211.FFFF 128 KB SFB ASIC control registers 1.C212.0000 1.C213.FFFF 128 KB Reserved 1.C214.0000 1.C217.
Table 14 (Cont.) CXTurbo Address Map Start Address End Address Size Description Discussed In 500 Models 1.E200.0000 1.E20F.FFFF 1 MB Reserved, System FEPROM Section 6.6 1.E210.0000 1.E211.FFFF 128 KB SFB ASIC control registers Section 6.3 1.E212.0000 1.E213.FFFF 128 KB Reserved 1.E214.0000 1.E217.FFFF 256 KB GP0 - general purpose output bit 0 1.E218.0000 1.E21B.FFFF 256 KB GP1 - general purpose output bit 1 1.E21C.0000 1.E21F.FFFF 256 KB RAMDAC color map and registers 1.E220.
6.3 Frame Buffer Control Registers Table 15 lists the addresses, size, and access mode of the frame buffer control registers: Table 15 Frame Buffer and Video Register Map Start Address Size Register Access 300 Models 1.C210.0000 32 bits Copy buffer register 0 R/W 1.C210.0004 32 bits Copy buffer register 1 R/W 1.C210.0008 32 bits Copy buffer register 2 R/W 1.C210.000C 32 bits Copy buffer register 3 R/W 1.C210.0010 32 bits Copy buffer register 4 R/W 1.C210.
Table 15 (Cont.) Frame Buffer and Video Register Map Start Address Size Register Access 500 Models 1.E210.0000 32 bits Copy buffer register 0 R/W 1.E210.0004 32 bits Copy buffer register 1 R/W 1.E210.0008 32 bits Copy buffer register 2 R/W 1.E210.000C 32 bits Copy buffer register 3 R/W 1.E210.0010 32 bits Copy buffer register 4 R/W 1.E210.0014 32 bits Copy buffer register 5 R/W 1.E210.0018 32 bits Copy buffer register 6 R/W 1.E210.
6.4 SFB ASIC Functions Software setup of these registers controls the video and functional components of the SFB ASIC. The following sections describe all registers and their format and initialization state Start Address Size Register Access Discussed In 300 Models 1.C210.0000 32 bits Copy buffer register0 R/W 1.C210.0004 32 bits Copy buffer register1 R/W 1.C210.0008 32 bits Copy buffer register2 R/W 1.C210.000C 32 bits Copy buffer register3 R/W 1.C210.
Start Address Size Register Access Discussed In 500 Models 1.E210.0000 32 bits Copy buffer register0 R/W 1.E210.0004 32 bits Copy buffer register1 R/W 1.E210.0008 32 bits Copy buffer register2 R/W 1.E210.000C 32 bits Copy buffer register3 R/W 1.E210.0010 32 bits Copy buffer register4 R/W 1.E210.0014 32 bits Copy buffer register5 R/W 1.E210.0018 32 bits Copy buffer register6 R/W 1.E210.001C 32 bits Copy buffer register7 R/W 1.E210.0020 32 bits Foreground R/W 1.E210.
6.4.1 Mode Register The setting of the MODE field determines what function the ASIC performs when it receives a write operation to the frame buffer address space.
The SFB ASIC maintains a flag to indicate if this address is a source or destination. The first write indicates a source; the second write indicates a destination. The state bit toggles back and forth between the two: subsequent write addresses supplied to the frame buffer in copy mode appear alternatively as source and destination addresses. To ascertain the state of the toggle bit, software performs a write operation to the Pixel Shift register and resets the copy engine to expect a source address.
BRES2 (Bresenham register 2) This register contains the address increment and error increment for the case of a non-negative error value. This error increment is a positive value which is subtracted from the base error value. Note Value at initialization: 0 The register’s format and contents are: 31 16 15 ADDRESS INCREMENT 2 00 ERROR INCREMENT 2 MR−0085−93RAGS BRES3 (Bresenham register 3) This register contains the initial error value for the Bresenham line draw algorithm.
In either case, the line continues for the number of iterations specified in the LineLength field of BRES3; and the data for the line is taken from the low order 16 bits of the input data. At the end of the line, the potential next pixel address for the line is saved and the LineLength is reset to 0. A write operation to the BCONT register continues this line for 16 more iterations. 6.4.
6.4.3 Raster Op Register The raster operation register is used in identifying the final value for the destination pixel. In many cases, it is some logical function such as source pixel xor destination pixel that gives the final pixel value. By using the raster operation register, the hardware can identify which operations will be write operations, rather than performing the entire read/modify/write operation on the pixel.
6.4.4 PixelMask Register The PixelMask Register is used in opaque stipple mode to determine which pixels are to be operated on. Each bit of the register corresponds to one pixel. If a bit is set, the corresponding pixel is affected by a stipple operation. If the bit is not set, the corresponding pixel is unaffected by a stipple operation. At initialization and at the end of each operation the entire contents of the PixelMask Register are set to 1s.
6.4.6 PixelShift Register The PixelShift value is used in copy mode only. The PixelShift defines which one of 16 shift values is performed on data before it is written into the copy buffer. The shift value is either negative or positive, based on the most significant bit of the PixelShift. A 1 in the most significant bit signifies a negative shift amount and a negative address increment.
6.4.9 START, BCONT, VIDEO_VALID, ENABLE_INTERRUPT, CLEAR_INTERRUPT Registers When written to, these registers change the ASIC: • START causes the address in the ADDRESS register to be used for the next write operation. • BCONT uses a pre-generated address from the former instruction as start address for the next instruction. • VIDEO_VALID signals that the TURBOchannel writes to the video registers have completed and video operations may begin.
6.4.10.1 Video Refresh Counter Register The contents of this register is used to store the interval between refresh reads. Each VRAM must be accessed within an 8-ms interval. There are 512 VRAM rows, and the clock used for the refresh count is the video shift clock or 1/4 multiple of the video oscillator frequency. The refresh count is (8 ms / 512) * ((1/interleave) * video oscillator).
6.4.10.3 Horizontal Setup Register This register contains all of the timing parameters required for the Video State machine horizontal control. These counters count in units of four pixels. The minimum value for these horizontal timing fields is two (giving a minimum of 8 pixel clocks for any field).
6.4.11 TCCLK COUNT, VIDCLK_COUNT Registers In order to determine which values to load into the video registers, there are two counters in the SFB ASIC. One counter counts 256 TURBOchannel clock cycles and the other counts video clock cycles, so that software can determine the oscillator frequency. Order to do this, software performs these operations: 1. Write the TURBOchannel clock address. This write operation resets the video clock counter and the TURBOchannel clock counter.
6.5 Bt459 RAMDAC The CXTurbo option uses the Bt459 RAMDAC in conjunction with a clock generator chip for sourcing the 8-plane RGB data. Below are details for writing the RAMDAC color map and control registers. For more information on the Bt459, see the manufacturer’s Bt459 RAMDAC Specification. The Bt459 supports a cursor function and three 256x8-bit color maps for its red, green, and blue video DACs.
Address Reg[15:0] Register 300 Models 0304 Cursor (y) high register 0305 Window (x) low register 0306 Window (x) high register 0307 Window (y) low register 0308 Window (y) high register 0309 Window width low register 030A Window width high register 030B Window height low register 030C Window height high register 030D - 03FF Reserved 0400 - 07FF Cursor RAM CXTurbo Graphics Subsystem: 300/500 Models 6–21
Address Reg[15:0] Register 500 Models 0000 - 00FF Color map 0100 - 01FF Overlay color register 0 - 15 0180 - 0184 Cursor color register 1 - 3 0200 ID register (always read as 4A) 0201 Command reg 0 0202 Command reg 1 0203 Command reg 2 0204 Pixel read mask register 0205 Reserved 0206 Pixel blink mask register 02007 Reserved 0208 Overlay read mask register 0209 Overlay blink mask register 020A Interleave register 020B Test register 020C Red signature register 020D Green sig
Updating the Bt459 Color Map To write the color map, load the Bt459’s address register low byte with the desired color map entry address (0000...00FF). Write the red, green, and blue values in three successive RAMDAC write operations to the color map. After the blue value is written, the Bt459 automatically increments the address register low byte to the next color map location. The same sequence may be repeated 256 times to update the color map fully.
6.6 System FEPROM (500 Models) Half of system ROM in the 500/500S models is addressable through the SFB ASIC at Dense I/O space locations 1.E200.0000-1E20F.FFFF. It is also addressable through Sparse I/O space. For both read and write operations, each ROM byte is mapped to a longword in I/O space. For example, to read ROM byte number 1, you must perform a read operation to Dense I/O space offset 1.E200.0004. Longword read operations to these addresses return a single byte in the low order byte.
7 IOCTL ASIC and System Registers The IOCTL ASIC controls the JUNKIO subsystem by moving data between its 16-bit I/O bus and the TURBOchannel. It provides an I/O read and write path from the CPU to the JUNKIO devices and a DMA path to memory for those devices that require it. Figure 9 shows the IOCTL subsystem. (Table 16 lists the IOCTL address map.
The IOCTL ASIC services requests from the following: • The TURBOchannel (I/O read or write) • Local Area Network Controller for Ethernet (LANCE) DMA • Integrated Services Digital Network (ISDN) DMA • Two possible serial DMA requests The IOCTL ASIC processes one request at a time granting the requests on a fixed priority basis. The IOCTL ASIC provides address pointers (for DMA), but no transfer length information, since transfer length counters already exist in the peripheral devices.
7.1 IOCTL Address Map Table 16 lists the I/O space allocation. Table 16 IOCTL Address Map Start Address End Address Size Register R/W 400/500/600/700/800/900 Models 1.E000.0000 1.E003.FFFF 256 KB System FEPROM (Section 7.2) R/W 1.E004.0000 1.E007.FFFF 256 KB IOCTL registers (Section 7.3) R/W 1.E008.0000 1.E00B.FFFF 256 KB Ethernet address ROM R 1.E00C.0000 1.E00F.FFFF 256 KB LANCE Ethernet interface R/W 1.E010.0000 1.E013.FFFF 256 KB SCC0 (A and B channels) R/W 1.E014.0000 1.
7.2 System FEPROM Depending on the setting of SSR<26>, The IOCTL can perform single-byte read and write operations or quad-byte read operations with the system ROM. • SSR<26>=0 Four read operations are performed on an 8-bit wide ROM. The IOCTL places the four bytes in one 32-bit word, with the first byte in the least significant byte position. A longword is returned to the CPU, and software reads the ROM one longword at a time. • SSR<26>=1 A single ROM access is enabled.
7.3 IOCTL Registers Address Map IOCTL ASIC registers are located: Address Description Discussed In 400/500/600/700/800/900 Models 1.E004.0000 Reserved 1.E004.0010 Reserved 1.E004.0020 LANCE DMA pointer Section 7.3.1 1.E004.0030 Serial comminucation transmit port 1 DMA pointer Section 7.3.2 1.E004.0040 Serial communication receive port 1 DMA pointer Section 7.3.3 1.E004.0050 Printer transmit port DMA pointer Section 7.3.4 1.E004.0060 Printer receive port DMA pointer Section 7.3.5 1.
Address Description Discussed In 300 Models 1.A004.0000 Reserved 1.A004.0010 Reserved 1.A004.0020 LANCE DMA Pointer Section 7.3.1 1.A004.0030 Serial comminucation transmit port 1 DMA Pointer Section 7.3.2 1.A004.0040 Serial communication receive Port 1 DMA Pointer Section 7.3.3 1.A004.0050 Printer transmit port DMA pointer Section 7.3.4 1.A004.0060 Printer receive port DMA pointer Section 7.3.5 1.A004.0070 Reserved 1.A004.0080 ISDN transmit DMA pointer Section 7.3.6 1.A004.
7.3.1 LANCE DMA Pointer Register (LDP)—1.A004.0020/1.E004.0020 The register’s format and contents are: Bits Access Reset Function 4:0 R/W UNP DMA physical address <33:29> 19:5 R/W UNP LANCE DMA physical address <16:2>, LANCE Address <15:1> 31:20 R/W UNP DMA physical address <28:17> Bits Function 4:0 The upper 5 bits of the pointer that the DMA engine uses to access the network buffer; can be changed only by writes from the CPU.
7.3.4 Printer Port Transmit DMA Pointer—NA/ 1.E004.0050 Unused in 300 models. This pointer points to the word containing the next byte to be transmitted through the printer port. The register’s format and contents are: Bits Access Reset Function 4:0 R/W UNP DMA physical address <33:29> 31:5 R/W UNP DMA physical address <28:2> 7.3.5 Printer Port Receive DMA Pointer—NA/1.E004.0060 Unused in 300 models. This pointer points to the word to contain the next byte to be received from the printer port.
7.3.8 ISDN Receive DMA Pointer—1.A004.00A0/1.E004.00A0 This is the address that the ISDN DMA uses when receiving data intended for main memory. This register is undefined at power up and must be loaded with the appropriate value before DMA. The register’s format and contents are: Bits Access Reset Function 4:0 R/W UNP DMA physical address <33:29> 31:5 R/W UNP DMA physical address <28:2> 7.3.9 ISDN Receive DMA Buffer Pointer—1.A004.00B0/1.E004.
7.3.11 System Support Register—1.A004.0100/1.E004.0100 The system support register (SSR) can be both read and written. Bits <31:16> are used inside the IOCTL ASIC. Bits <15:0> generate signals visible outside the IOCTL ASIC. The register’s format and contents are: Bits Access Reset Function 3:0 R/W 0 In 300 models, are programmed to provide the byte mask during read operations on the TURBOchannel. Byte Reads are allowed only during Sparse Space accesses.
Bits Access Reset Function 15 R/W 0 10Base-T TPIC Test Mode. For testing purposes. Must be clear (default) in normal operation. Must be 1, if the 10Base-T loopback connector is installed. 16 R/W 0 LANCE DMA enable. When set, enables LANCE DMA, so that the Ethernet can begin functioning; when clear, disables same. 17 Reserved 18 Reserved 19 R/W 0 ISDN receive DMA enable. When set , enables the ISDN receive DMAs; when clear, disables same. 20 R/W 0 ISDN transmit DMA enable.
7.3.12 System Interrupt Register (SIR)—1.A004.0110/1.E004.0110 The SIR consists of two sections. • Bits <31:16> are set by the DMA engine for various DMA conditions. These bits are always set by the system and can be cleared by writing a 0 to them. Writing a 1 has no effect. These Bits are cleared to 0 during system powerup /reset. • Bits <15:0> reflect the status of specific system devices and are read-only. A few are not usually used as interrupts and should be masked.
Bits Access Function 13 R ISDN Interrupt This bit records the state of the interrupt from the ISDN audio chip. Set when the 79C30A needs interrupt service. Updated every 125 s, remains active until the ISDN audio chip interrupt register is read or the ISDN audio chip is reset.
Bits Access Function 24 R/W0C In 300 models, reserved. In 400/500/600/700/800/900 models, printer port receive DMA overrun This bit is set and the DMA disabled, as soon as the receive DMA pointer associated with printer port reaches a page boundary. To restart, this bit must be cleared by writing a 0; writing a 1 has no effect. Note that bit <25> is set whenever this bit is set.
Bits Access Function 31 R/W0C Communication port 1 (SCC0) transmit page end interrupt When set, disables DMA. When clear, enables DMA. When enabled, the DMA transmitter transmits bytes until the pointer reaches a 4-KB page boundary. It then stops DMA and interrupts the processor. To restart, this bit must be cleared by writing 0; writing 1 has no effect. 7.3.13 System Interrupt Mask Register—1.A004.0120/1.E004.
7.3.15 ISDN Data Transmit Register—1.A004.0140/1.E004.0140 This register contains the data that are transferred from memory during DMA. The data is loaded into the transmit shift register (see Section 9.5.2.8 for more detail.) The register’s format and contents are: Bits Access 23:0 R/W 31:24 Reset Function UNP ISDN transmit data 0 Reserved, returns 0 when read 7.3.16 ISDN Data Receive Register—1.A004.0150/1.E004.
7.3.18 SCC-0 DMA Slot Register—1.A004.0180/1.E004.0180 This and other DMA slot registers were included in the hardware for future implementations of the address decoding. The register’s format and contents are: Bits Access Reset Function 3:0 R/W UNP Chip selects. Must be set to 4; otherwise, registers cannot be written to. 9:4 R/W UNP Hardware address supplied for SCC-0 DMA accesses. Must be set to 1. Control hardware decoding of addresses supplied for SCC-0 DMA accesses.
7.4 Ethernet Station Address ROM Addresses The ROM consists of 32 8-bit locations and is longword-aligned. The data is presented on byte 0 (0-7) of the data bus. Table 19 lists Ethernet station address ROM addresses for the 400/500/600/700 /800/900 models. Table 20 lists Ethernet station address ROM addresses for the 300 models. Table 19 Ethernet Station Address ROM Addresses (400/500/600/700/800/900 Models) Address Content Value 1.E008.0000 Address octet 0 1.E008.0004 Address octet 1 1.E008.
Table 19 (Cont.) Ethernet Station Address ROM Addresses (400/500/600/700/800 /900 Models) Address Content Value 1.E008.0078 TEST Pattern 6 55 1.E008.007C TEST Pattern 7 AA Table 20 Ethernet Station Address ROM Addresses (300 Models) Address Content Value 1.A008.0000 Address octet 0 1.A008.0004 Address octet 1 1.A008.0008 Address octet 2 1.A008.000C Address octet 3 1.A008.0010 Address octet 4 1.A008.0014 Address octet 5 1.A008.0018 Chksum octet 1 1.A008.001C Chksum octet 2 1.A008.
Table 20 (Cont.) Ethernet Station Address ROM Addresses (300 Models) Address Content Value 1.A008.
7.5 LANCE Register Addresses Table 21 lists LANCE register addresses for the 400/500/600/700/800/900 models. Table 22 lists LANCE register addresses for the 300 models. Table 21 LANCE Register Addresses (400/500/600/700/800/900 Models) Address Register 1.E00C.0000 LANCE_RDP 1.E00C.0004 LANCE_RAP Table 22 LANCE Register Addresses (300 Models) Address Register 1.A00C.0000 LANCE_RDP 1.A00C.0004 LANCE_RAP 7.6 SCC Register Addresses Table 23 lists SCC register addresses for the 300 models.
Table 24 (Cont.) SCC Register Addresses (400/500/600/700/800/900 Models) Address Register 1.E018.0008 SCC(1)-A keyboard RAP 1.E018.
7.7 RTC Register Addresses Table 25 lists RTC register addresses for the 300 models. Table 26 lists RTC register addresses for the 400/500/600/700/800/900 models. Table 25 RTC Register Addresses (300 Models) Address Register Description Range 1.A020.0000 RTC_SEC Seconds 0..59 1.A020.0004 RTC_ALMS Seconds alarm 0..59 1.A020.0008 RTC_MIN Minutes 0..59 1.A020.000C RTC_ALMM Minutes alarm 0..59 1.A020.0010 RTC_HOUR Hours 0..23 1.A020.0014 RTC_ALMH Hours alarm 0..23 1.A020.
7.8 ISDN Register Addresses To read from or write to indirect register, first write an indirect address command to the command register (CR). One or more data bytes may then be transferred to or from the selected register through the data register (DR). Section 7.8.2 lists ISDN register addresses for the 400/500/600/700/800/900 models. Section 7.8.1 lists ISDN register addresses for the 300 models. 7.8.
Table 28 (Cont.
Table 28 (Cont.) ISDN Indirect Address Registers (300 Models) Address Register Name R/W 9216 Extended FIFO control EFCR R/W C016 Peripheral port control 1 PPCR1 R/W C116 Peripheral port status PPSR R C216 Peripheral port int.
Table 30 ISDN Indirectly Addressed Registers (400/500/600/700/800/900 Models) Address Register Name R/W 2116 INIT R/W 2016 INIT2 R/W A116 LIU status LSR R A216 LIU priority LPR R/W A316 LIU mode register 1 LMR1 R/W A416 LIU mode register 2 LMR2 R/W A516 - Perform 2-4 - A616 Multiframe MF R/W A716 Multiframe S-bit/status MFSB R A816 Multiframe Q-bit buffer MFQB W 4116 MUX command register 1 MCR1 R/W 4216 MUX command register 2 MCR2 R/W 4316 MUX command regis
Table 30 (Cont.) ISDN Indirectly Addressed Registers (400/500/600/700/800/900 Models) Address Register Name R/W 8716 D-channel mode register 2 DMR2 R/W 8816 - Perform 1-7 - 8916 D-channel receive byte count DRCR R 8A16 Random number generator RNGR1 (LSB) R/W 8B16 Random number generator RNGR2 (MSB) R/W 8C16 First rcvd byte addr. reg. 4 FRAR4 R/W 8D16 Second rcvd byte addr. Reg.
8 TURBOchannel Dual SCSI ASIC The TURBOchannel Dual SCSI ASIC interfaces the TURBOchannel using the NCR 53C94 Advanced SCSI Controller in the 300/400/500 models and the 53CF94-2 Advanced SCSI Controller in the 600/700/800/900 models.
8.1 TURBOchannel Dual SCSI Address Map Table 31 lists the distribution of I/O space. Table 31 TURBOchannel Dual SCSI Address Map Start Address End Address Size Space 400/500/600/700/800/900 Models 1.C000.0000 1.C003.FFFF 256 KB FEPROM 1.C004.0000 1.C007.FFFF 256 KB Internal registers 1.C008.0000 1.C00B.FFFF 256 KB SCSI registers 1.C00C.0000 1.C00F.FFFF 256 KB DMA buffers 300 Models 1.8000.0000 1.8003.FFFF 256 KB FEPROM 1.8004.0000 1.8008.0000 1.8007.
8.2 Internal Registers The Dual SCSI internal registers control DMA transfers and reflect their status. The registers are located: Table 32 TURBOchannel Dual SCSI ASIC Register Map Start Address End Address Size Register R/W 300 Models 1.8004.0000 1.8004.0003 4B Control interrupt register (Section 8.2.1) R/W 1.8004.0004 1.8004.0007 4B 1.8004.0008 1.8004.0FFF Interrupt mask enable Register (Section 8.2.2) R/W 1.8004.1000 1.8004.1003 4B SCSI[0] DMA address (Section 8.2.3) R/W 1.8004.
8.2.1 Control Interrupt Register (CIR)—1.8004.0000/1.C004.0000 The control interrupt register (CIR) consists of two sections: • The most significant 16 bits are the interrupt section. These bits are set by hardware and can be cleared only by the system writing 0; writing 1 has no effect. • The less significant 16 bits are the control section. Parity test mode forces bad parity instead of the normal odd-generated parity. SCSI resets terminate the current DMA transaction.
Bit Access Reset Description 12 R/W 0 In 300 models, Reserved. 300 models do not support TURBOchannel parity. In 400/500/600/700/800/900 models, SCSI[0] DMA buffer parity test mode; when set, bad parity is written into the SCSI[0] DMA buffer during DMA receives from the 53C94. During DMA reads, parity always comes from the TURBOchannel. This allows bad parity to be asserted on the TURBOchannel during DMA write data cycles. 13 R/W 0 SCSI[1] In 300 models, Reserved.
Bit Access Reset Description 24 R/W0C 0 SCSI[0] DB parity error Set when a parity error is detected during a 53C94 /53CF94-2 DMA receive data cycle or an I/O read of the FIFO for SCSI[0]. 25 R/W0C 0 SCSI[1] DB parity error Set when a parity error is detected during a 53C94 /53CF94-2 DMA receive data cycle or an I/O read of the FIFO buffer for SCSI[1]. 26 R/W0C 0 SCSI[0] DMA buffer parity error Set when a parity error is detected during a read of the SCSI[0] DMA buffer.
8.2.2 Interrupt Mask Enable Register (IMER)—1.8004.0004/1.C004.0004 The IMER consists of two 16-bit sections: the 16 most significant bits are the interrupt mask; the 16 least significant bits are the interrupt enable. • The Interrupt Mask Bits (IMER<31:16>) report bits set in the interrupt register to the TURBOchannel.
8.2.3 SCSI[x] DMA Address Register (SDAx)—1.8004.1x00/1.C004.1x00 The SDAx is the longword DMA address. It increments as data leaves the ASIC and can be polled to indicate the address of data to be transferred next. At the end of a transfer, it holds the address of the remaining unaligned data. If another DMA transfer continues the previous one and the transfer count was a multiple of four bytes, the address need not be reloaded.
8.2.4 SCSI[x] DMA Interrupt Control Register (DICx0)—1.8004.1x04/1.C004.1x04 The DICx consists of four 8-bit sections. The lowest byte controls the DMA; the three high bytes are reserved.
8.2.5 SCSI[x] DMA Unaligned Data[0] (DUDx0)—1.8004.1x08/1.C004.1x08 The DUDx0 is the buffer for the first 1-3 bytes of unaligned data for DMA writes to memory. It must be read if the DMA address<1:0> does not contain 00. The bytes appear in the correct byte locations. When set to 1, mask bits 0-3 indicate that the corresponding byte contains valid data. The least significant bit is always 0.
8.2.6 SCSI[x] DMA Unaligned Data[1] (DUDx1)—1.8004.1x0C/1.C004.1x0C The DUDx1 is the buffer for the last 1-3 bytes of unaligned data for DMA writes to memory. It must be read if the transfer did not end on a longword boundary. The bytes appear in the correct byte locations. When set to 1, mask bits 24-26 indicate that the corresponding byte contains valid data. Bit three is always clear.
8.3 NCR 53C94 Registers (300/400/500 Models) The 53C94 registers are accessed as bits<7:0> of the addressed longword. Each register is addressed by adding the offset listed in the next table to the base address listed in the next table. Write operations to the remaining bits are ignored, and read operations are UNPREDICTABLE. The TURBOchannel byte mask is ignored write operations to these registers. Use of these registers is described in Section 9.6.3.
8.4 NCR 53CF94-2 Registers (600/700/800/900 Models) The 600/700/800/900 models use the 53CF94-2 SCSI controller device, which provides these systems with optional Fast SCSI as defined by the ANSI standard, which provides a data rate up to 10MB/s in synchronous mode. GPI bit <2> (readable in CIR<6>) reports the SCSI chip oscillator frequency. A value of 0 indicates that the oscillator is 40 MHz and that Fast SCSI data transfers have been enabled through the console.
8.5 DMA buffers The DMA buffers are 32 longwords in size for each SCSI. Access to these buffers is for diagnostic purposes; otherwise, driver software need not access them. Write operations to these longwords ignore the byte mask: the entire longword is written. These buffers are cleared when the DMA engine is reset. The buffers’ location, format, and contents are: Start Address End Address Size Register R/W 400/500/600/700/800/900 Models 1.C00C.0000 1.C004.007F 128 B SCSI[0] DMA buffer R/W 1.
9 I/O Programming This chapter describes programming considerations and restrictions for I/O transactions. It covers the following topics: • I/O read and write restrictions (Section 9.1) • DMA (Section 9.2) • Interrupt handling during I/O operations (Section 9.3) • TURBOchannel usage—system-specific (Section 9.4) • JUNKIO subsystem (Section 9.5) • SCSI interface (Section 9.
9.1 I/O Read and Write Restrictions Several restrictions apply to I/O operations. • Read operations performed on reserved locations or read operations performed on write-only bits, result in UNPREDICTABLE data being returned. • Write operations performed on reserved locations or write operations performed on read-only bits result in UNPREDICTABLE data being written to UNPREDICTABLE locations.
9.2 DMA DMA transactions differ in length requirements according to their source: • DMA transactions performed by an adapter may be of any length, for example a 10-block transfer from a disk. The adapter divides these transfers into multiple TURBOchannel DMA bursts. • Individual DMA bursts on the TURBOchannel can be no longer than 64 longwords (on 300 models) or 128 longwords (on 400/500/600/700/800/900 models) and cannot cross a 2 KB boundary. 9.2.
9.3 Interrupt Handling During I/O Operations You may receive unexpected interrupts, because of a race condition between a Write To Clear an Interrupt (WTCI) instruction and a Read of the Interrupt Register (RIR) instruction to check for further interrupts. To prevent such interrupts, insert code between the WTCI and the RIR. Digital recommends the following code sequence: 1. Write to clear interrupt. 2. Create a memory barrier. 3. Read something from the TURBOchannel, ignoring results—for example, 1.F008.
9.4 TURBOchannel Usage (System-Specific) The following sections discuss TURBOchannel usage on 300 models and on 400/500/600/700/800/900 models: • DMA size (Section 9.4.1) • DMA arbitration (Section 9.4.2) • I/O timeout (Section 9.4.3) 9.4.
• No timeouts occur during DMA arbitration. 9.4.2.2 DMA Arbitration (400/500/600/700/800/900 Models) Priority is determined by means of a binary tree of priority selectors. Based on its own state, each selector (p#) determines which of its two inputs has priority. Whenever ACK is generated, each selector in the priority path sets its next state to give priority to the opposite input request.
9.4.4 I/O Conflicts The TURBOchannel protocol allows a device that cannot handle the current I/O transaction to signal a conflicted I/O transaction to the system. In this case, the conflicted I/O transaction is retried until it completes either through acknowledgment or timeout. Use the option of signalling a conflicted transaction only to avoid deadlock, because no other I/O request can be handled until the conflicted one is satisfied.
9.5 JUNKIO Subsystem The JUNKIO uses the IOCTL ASIC as the bus interface connecting the TURBOchannel to a 16-bit general purpose I/O bus. This bus services the following devices: • AMD 7990 (LANCE) • Zilog Z85C30 (SCC) • Dallas Semiconductor DS1287A Real-Time Clock (RTC) • AMD 79C30A (ISDN) • FEPROMs 300 models: 768 KB 400/500/600/700/800/900 models: 256 KB All I/O accesses to the devices are identical, except accesses to the Local Area Network Contoller for Ethernet (LANCE).
Bits <31:16> reflect various DMA conditions; bits <15:0> reflect the status of specific system devices and may be individually masked. See Section 7.3.12 for further information. • SSR Bits <31:16> enable DMAs and determine the direction of some types of DMA transfers. See Section 7.3.11 for further information. 9.5.2 I/O Programming and System FEPROM JUNKIO FEPROMs differ according to model. • 300 models contain 768 KB of Flash ROMs, configured as 3 different 256-KB Flash ROMs.
The LANCE registers are 16 bits wide and longword-aligned. For example, a write operation to a register of 12345678 will write 5678 into that register. Likewise, if a register contains 5678 then a read operation of that register returns xxxx5678, where x = UNPREDICTABLE data. LANCE programmed I/O cannot be performed if incorrect information about the LANCE I/O slot register is provided to the IOCTL subsystem. Further information about LANCE registers can be found: Section 7.3.
Table 33 Baud Rate Programming Baud Divider Value 19.2 K 1610 10 9600 1610 22 7200 1610 30 4800 1610 46 3600 1610 62 2400 1610 94 2000 1610 113 1800 1610 126 1200 1610 190 600 1610 382 300 1610 766 150 1610 1534 134 1610 1717 110 1610 2093 75 1610 3070 50 1610 4606 The SCC registers are aligned to longwords with data being read and written from byte 1. For example writing a 0x01234567 to an SCC register sets it to a value of 45.
9.5.2.6 DMA for Communication Receive Port and Printer Port Receive DMA writes a longword containing data in byte 1 of the location specified by the receive pointer; the pointer is then incremented. When the DMA begins filling the second half of a 4 KB page, an interrupt is generated to indicate that the buffer is filling up. Software should disable DMA, allocate a new page buffer, and update the pointer before restarting DMA. If an error occurs and ends a DMA, error information is reported in the SIR.
2. The next write or read operation to the RAP writes to or reads from the register pointed to by the RAP. After this operation is completed the RAP is cleared. (If you are uncertain about the state of the RAP, perform read operations on it until it returns zeros.) Section 7.6 lists SCC register addresses. 9.5.2.
9.5.2.9 ISDN DMA ISDN has both a receive and a transmit address pointer and address buffer pointer. These prevent DMA stalling, if software could not load a new address in a timely manner. If an ISDN transmit DMA pointer crosses a page boundary, the transmit buffer pointer is loaded into the transmit pointer, and an interrupt is set. This directs software to reload the buffer pointer.
9.6 SCSI Interface This section, which describes the use of the Dual SCSI ASIC, covers the following topics: • Differences among 300, 400/500, and 600/700/800/900 models (Section 9.6.1) • Dual SCSI ASIC configuration (Section 9.6.2) • 53C94 configuration and programming (Section 9.6.3) • 53CF94-2 configuration and programming (Section 9.6.4) • Initiation of DMA transfers (Section 9.6.5) • Aborting Transactions (Section 9.6.6) 9.6.
Determining SCSI Oscillator Frequency The TURBOchannel Dual SCSI ASIC (TCDS) has four general purpose input (GPI) bits, which are readable in its CIR register bits <7:4>. GPI bit <2> (readable in CIR<6> has been reserved to report the SCSI chip oscillator frequency. A value of 1 indicates that the oscillator is 25 MHz as in the 300 /400/500 models.
Selection of Fast or Slow SCSI Provision has been made to allow operator selection of Fast SCSI transfer rates, through nonvolatile flags setable through the console. Software and Firmware can inspect these flags, one per SCSI bus, to determine the maximum transfer rate (5 or 10 MB/s). This is done through the use of the SCSI Synchronous Data Transfer Rate negotiation. At time of manufacture, the flags will default to Slow SCSI to ease a system upgrade where existing SCSI devices and cables are to be used.
00 07 X X X X X C C F MR−0184−93RAGS Field Value Description CCF 101 25 MHz CCF 000 40 MHz X Reserved DMA transactions require programming of the 53C94 and 53CF94-2. Refer to the NCR 53C94-95-96 Advanced SCSI Controller or NCR 53CF94/96-2 Fast SCSI Controllerfor its programming. The ASIC must be programmed before the 53C94 or 53CF94-2. 9.6.5 Initiation of DMA Transfers Two registers must be written before a transfer begins: • The DMA Address Register (Section 8.2.
9.6.5.1 Unaligned DMA Write Operation Two registers are provided for unaligned data during DMA writes: • DMA unaligned data[0] (Section 8.2.5) DMA unaligned data[0] contains the unaligned data at the beginning the transfer. The least significant byte has a mask for writing this data to memory. The address is the DMA address that was originally written to the ASIC. This address must be made available to software. • DMA unaligned data[1] (Section 8.2.
10 Hardware Exceptions and Interrupts This chapter discusses the behavior of the system under hardware exceptions and interrupts. Emphasis is placed on interrupts caused by errors as well as by exceptions. The chapter also discusses interrupts not caused by errors, such as interrupts of I/O devices. The chapter covers the following topics: • Sources of errors and interrupts (Section 10.1) • Behavior of system hardware under errors (Section 10.2) • System error/interrupt matrix (Section 10.
10.1 Sources of Errors and Interrupts Several functional units are equipped for detecting and reporting errors. These are: • CPU (CPU)—ECC tree built in, plus internal error detection hardware • TURBOchannel adapter (TC)—ECC tree for memory bus and parity tree for scatter/gather map and TURBOchannel • Bcache Controller (BCtl)—parity tree for Bcache tags • TURBOchannel options—parity trees for TURBOchannel • Dual SCSI ASIC (TCDS)—parity trees for SCSI adapters, TURBOchannel and internal buffers.
Table 36 lists the available detection of data transfers within the system.
10.2 Behavior of System Hardware Under Errors When an exception or interrupt occurs, the CPU empties its execution pipeline, loads the current PC into the EXC_ADDR IPR, and dispatches to an exception PAL routine. If multiple exceptions occur, the CPU dispatches to the highest priority applicable PAL entry point. The PAL entry point is specified as the value of PAL_BASE IPR plus a condition-specific offset. Table 37 lists the entry points from highest to lowest priority.
10.3 System Error/Interrupt Matrix This section discusses interrupts and hardware-caused machine checks. Exceptions—encompassing faults, arithmetic traps, and synchronous traps—are not discussed. All interrupt flows include PALcode’s construction of an interrupt stack frame, as shown in Figure 11.
Figure 12 Corrected Error (Small) Logout Frame 63 47 R SYSTEM OFFSET = [170#16] 31 15 BYTES[1E0#16] PROCESSOR OFFSET = [118#16] :+000#16 :+008#16 MACHINE CHECK ERROR CODE :+010#16 BIU_STAT BIU_ADDR DC_STAT FILL_SYNDROME FILL_ADDR BC_TAG INTR/EXCEP IDENT :+148#16 MR−0107−93RAGS Figure 13 Machine check (large) logout frame 63 47 31 R 15 BYTES[1E0#16] SYSTEM OFFSET = [170#16] :+000#16 PROCESSOR OFFSET = [118#16] :+008#16 MACHINE CHECK ERROR CODE :+010#16 PAL TEMP REGISTERS [31:00]<63:00>
Table 38 System Error/Interrupt Matrix Error Code for Logout Frame What Happened, Who saw it, What they did, What is most likely broken, What else is possibly broken How Reported, PAL Entry Point 1 PAL Action NA HALT switch pushed CPU via HALT interrupt Dispatch to PAL Nothing Halt Interrupt 00E0 06=Rd 07=WR Bcache TPE during DMA Cache PALs DMA abort, See below Bcache tag store RAM BC external parity tree 08 SCB Offset2 IPL Dispatch to PAL_BASE + 0000 NA NA UnCorr Interrupt 00E0 See algorith
Table 38 (Cont.) System Error/Interrupt Matrix Error Code for Logout Frame What Happened, Who saw it, What they did, What is most likely broken, What else is possibly broken How Reported, PAL Entry Point 1 12 uncorr ECC error on DMA Rd TC ASIC DMA abort, see below main memory DRAMs memory connectors UnCorr Interrupt 00E0 13 I/O Write Data ECC error TC ASIC DMA abort,see below SLICE ASICs TC ASIC 14=Rd 15=Wr SCB Offset2 IPL Build stack Build large logout, R=~isr.
Table 38 (Cont.
Table 38 (Cont.) System Error/Interrupt Matrix Error Code for Logout Frame What Happened, Who saw it, What they did, What is most likely broken, What else is possibly broken How Reported, PAL Entry Point 1 NA Powerup 0000 PAL Action SCB Offset2 run reset code 1 All PAL entry points are relative to the contents of the PAL_BASE register. 2 All IPL 31 SCB entry points are relative to SCBB.
• Actions taken by hardware for a DMA abort: ~err -> option uncorr interrupt -> CPU error logged in FADR, TCEREG, and IR DMA is aborted • • • Actions taken by hardware for an I/O error: • uncorr interrupt -> CPU • error logged in FADR, TCEREG, and IR • write is aborted, bad read data is returned Actions taken by hardware for an invalid I/O address error: • uncorr interrupt -> CPU • error logged in FADR, TCEREG, and IR • reads and writes will have UNPREDICTABLE results Actions taken by hardw
10.4 Dual SCSI Error/Interrupt Matrix Table 40 lists and describes interrupts from the Dual SCSI.
Table 40 (Cont.
10.5 Error Insertion for Testing Purposes Certain hardware errors listed is Table 38 may be intentionally inserted in order to verify the checkers. Table 41 lists error codes and the corresponding errors’ insertion technique, where possible. Table 41 Error Insertion Techniques 01 - 04 None 06 - 07 Bad tag parity can be written to any Bcache tag by storing the tag to 8(address) in tag space. 08 Test modes in the Dual SCSI ASIC can be configured to cause this.
10.6 Assignment of CPU Interrupt Pins Six interrupt pins are provided on the CPU. These interrupts are decribed in Table 42. Table 42 Interrupt Pin Allocation IRQ Pin Definition IRQ[0] Unused IRQ[1] SysAD.IntTmr—interval timer interrupt IRQ[2] SysAD.CorrIntr—correctable interrupt from I/O adapter IRQ[3] SysAD.IOIntr— OR of all I/O option interrupt lines IRQ[4] SysAD.UnCorrIntr—uncorrectable interrupt from I/O adapter IRQ[5] SysAD.
10.8 PAL Recovery Algorithms for Selected Errors The following sections give examples of PAL recovery algorithms for the following selected errors: • Bcache tag error on DMA read/WRite (Section 10.8.1) • Bcache tag parity error on CPU reference, LDxL, STxC (Section 10.8.2) 10.8.1 Bcache Tag Error on DMA Read/Write DMA write operation tag parity errors may be signalled after data has been transferred, causing the TCEREG and FADR registers to lock with incorrect data.
10.8.
11 CPU Power Up and Initialization This chapter covers the following topics: • Processor initialization (Section 11.1) • Bcache initialization (Section 11.2) 11.1 Processor initialization Figure 14 shows the initialization process. Figure 14 Processor Initialization Block Diagram Power On CPU, ASICs, PALs Do Hardware Reset.
Pressing the HALT button causes entry into the system ROM code by means of a PAL halt, which further determines whether a HALT or a Reboot is required. Note HALT can be masked out. Refer to the DECchip 21064-AA Microprocessor Hardware Reference Manual under HIER. Chapter 13 discusses DEC 3000 firmware ROMs in detail. 11.1.1 Power-On Reset Sequence Upon assertion of RESET, the ASICs and PALs force their registers into a known state.
6. Polls the Ethernet subsystem for received packets that require servicing—for example, loop-back and generation of system identification packet 7. Execute PALcode. 8. Execute MIPS emulator. The last step concludes the initialization by the hardware and firmware. Control is now directed to the operating system, which performs its own initialization. 11.2 Bcache Initialization Bcache initialization is performed by the SROM code. The BTAGS are initialized by means of I/O space writes (see Section 2.6).
12 Firmware: Overview DEC 3000 firmware consists of these elements: • Power-up initialization code (Section 12.1) • A console program (Section 12.2) • Extended self-test code and utilities (Section 12.3) • Privileged architecture library code (PALcode) (Section 12.4) • A MIPS Emulator (Section 12.5) The firmware of all DEC 3000 models conforms to the description in this section with these differences: • Memory Subsytem Each bank is comprised of one side of two 32-bit data SIMMs.
Table 44 TURBOchannel Differences System TURBOchannel Option Slots 300L 0 300/300X/300LX 2 400/600/700 3 500/800/900 6 500X 5 • Diagnostic LEDs Table 45 lists diagnostic LED displays and locations.
12.1 Overview of Power-Up Initialization Code On powerup, the power-up initialization code is loaded from 8 KB of serial ROM into the Icache of the CPU. The initialization sequence is: 1. Perform any CPU-specific code. 2. Size the system memory. 3. Write the memory configuration to the bank configuration registers. 4. Find two good megabytes of memory, starting the search at the bottom of memory. • In 300 models, an error detected at this point is fatal.
12.2 Overview of the Console The console program operates a terminal device that may be one of the following: • A terminal connected to a serial port line (for example, the printer port) • A workstation display device and LK401 keyboard • A remote system connected over the Ethernet using MOP protocol. Chapter 16 describes the console program, operation, commands, and security measures. 12.
12.5 Overview of the MIPS Emulator The MIPS emulator creates an environment in which MIPS native instructions can be executed on the DEC 3000. The MIPS emulator consists of two components: an instruction emulator and the ROM Executive (REX) environment. These allow execution of any self-test, boot driver, or console driver that resides on a TURBOchannel option. Chapter 18 describes TURBOchannel support in greater detail.
13 DEC 3000 AXP Firmware ROMs This chapter covers the following topics: • DEC 3000 AXP firmware ROM format (Section 13.1) • System and I/O ROM contents (Section 13.2) • System ROM format (Section 13.3) 13.1 DEC 3000 AXP Firmware ROM Format The firmware is contained in three ROMs: • 64 KB Serial ROM • 256 KB System ROM (part of the SFB logic) in 500/800/900 systems only • 256 KB I/O Board ROM The CPU accesses the Serial ROM (SROM) one bit at a time.
• Console service routine(s) • Device configuration data • Ethernet Driver These firmware components reside in the I/O ROM: • SCSI Self-test/utilities • Ethernet self-test/utilities • ISDN/Audio self-test/utilities • CXT Self-test/utilities • SCC Self-test • Memory self-test • MIPS Emulator 13–2 DEC 3000 AXP Firmware ROMs
13.3 System ROM Format The system ROM is a 256 KB x 8 FLASH ROM that resides on the CXT logic of the DEC 3000 AXP system board. The I/O ROM is a 256 KB x 8 FLASH ROM connected to the COREIO chip on the system I/O board. Figure 15 shows the ROM header format.
The components of the ROM header are: Component Address Length Description ROM Width Base + 016 1 Byte The width of the ROM in bytes. The system ROM width is 1, while the I/O ROM width is 4. ROM Stride Base + 416 1 Byte The address stride of the ROM. This must be a 4. ROM Size Base + 816 1 Byte The size of the ROM in bytes divided by 8192. Slot Size Base + C16 1 Byte The minimum TURBOchannel slot size required by the option module divided by 4 194 304 (4 MB).
Component Address Length Description Flags Base + 9016 4 Bytes A 4-byte field with bit<0> indicating whether this module implements parity. A 1 in bit<0> means that this option supports TURBOchannel parity. All remaining bits are reserved and should remain zero. ROM Objects Base + A016 Variable size The data structures that provide information about a section of code or data in the ROM. The first ROM object in both the System ROM and the I/O ROM contains all the code that is present in the ROM.
Component Address Length Description Length ROM object base + 4 4 Bytes Length of the ROM object in bytes. This length must be a multiple of 4. Name ROM object base + 8 12 Bytes The name of the object in ASCII. Only graphic ASCII codes are allowed. Unused characters must contain blanks. Body ROM object base + 14 Variable The code and data that make up this ROM object.
14 Powerup Initialization and Firmware Entry When you power up the DEC 3000 AXP, the serial ROM code is loaded into the CPU’s 8 KB instruction cache. Serial ROM (SROM) code verifies the functionality of the hardware required to load and execute the system ROM code, which contains the PAL machine initialization and console code. After the Icache is loaded, the SROM data and clock lines are used to establish a serial-line connection to the CPU. An EIA adapter module provides the interface to terminal devices.
Figure 17 Power-On Initialization Flow Power Applied Serial ROM Code Decompress Code PAL Machine Reset Fixup Linkage Section Build Up HWRPB,SLOT...
Table 46 300 Model SROM Power-On Sequence LED Activity Meaning FF Power is on, loading SROM code into the DECchip 21064–AA CPU, starting the memory sizing routine. Several possibilities: CPU’s clock, power, DCOK, reset, IRQ, icMode, or other primordial wiring is faulty; blank or unprogrammed SROM. FE SROM is not coded to send FE to LEDs. FD Memory sizing completed FC SROM is not coded to send FC to LEDs. FB Initializing the 2 MB test range of memory to zeroes.
Table 46 (Cont.) 300 Model SROM Power-On Sequence LED Activity Meaning F1 Completed load of IOROM into memory. Reading state of jumper to see if SROM code should trap to the miniconsole instead of transferring execution to console code. Not coded to stop here. F0 SROM code execution completed normally. Execution transferred to console or miniconsole. Cannot execute console code, or the miniconsole jumper is set. (The mini-console is for Digital use only.) 20 Machine check Trap to miniconsole.
Table 47 (Cont.) 400/500/600/700/800/900 Model SROM Power-On Sequence LED Activity Meaning F5 Completed COREIO register test and init. Initializing all memory to zeroes followed by fetch of SYS ROM manufacturing data. Should never stop here. F4 Fetched SYS ROM manufacturing data. Loading contents of SYS ROM into memory. SYS ROM manufacturing data was bad. Fatal error. F3 Completed load of SYS ROM into memory. Fetching IO ROM manufacturing data. Should never stop here.
14.3 Map of Memory Following Power-Up Initialization Thirty-two megabytes of memory are tested on power up: two megabytes of memory are used for the system firmware and any required data; the remaining thirty megabytes will be used to load in secondary boot program. The first two megabytes of memory are always the lowest two megabytes of good memory.
Note The virtual ROM executive (REX) memory region is located at the bottom of memory, and the TURBOchannel options expect the REX memory region to reside in that physical location. For this reason the scatter /gather registers need not be used to perform DMA. 14.4 Machine State Following Power-Up Initialization Table 48 lists the values of several important registers following power-up initialization.
Table 48 (Cont.) Register Values After Power-Up Name Value Description COREIO ASIC Registers Ethernet DMA pointer Unknown The NI boot driver or NI console driver may have this pointing to its LANCE buffers whose address can not be determined. SCC0 XMIT DMA Ptr 0x00000000 Initialized to 0. SCC0 RCV DMA Ptr 0x00000000 Initialized to 0. SCC1 XMIT DMA Ptr 0x00000000 Initialized to 0. SCC1 RCV DMA Ptr 0x00000000 Initialized to 0. ISDN XMIT DMA Ptr 0x00000000 Initialized to 0.
Table 48 (Cont.) Register Values After Power-Up Name Value Description I/O Controllers SCC0, SCC1 Mouse and keyboard port are 4800 baud while communications and printer port are 9600 baud. All ports have 8-bit character, one stop bit, parity off. SCSI The SCSI controllers are reset by issuing a Reset Chip command to each controller. The controller registers are left in the reset state. Memory 0x00000000 All memory not loaded by the boot code is initialized to a pattern of 0x00000000. 14.
Example 2 System Firmware Entry Code if (halt code == powerup) { hlt_act = hlt_swx if (hlt_act == HALT) halt else boot } else if (halt code == external halt (HALT button)) halt (enter the console) else { case hlt_act RESTART: { hlt_act = hlt_swx restart using the address in the HWRPB } BOOT: { hlt_act = hlt_swx boot the machine using the default boot device } HALT: { hlt_act = hlt_swx halt (enter the console) } } Figure 19 shows the virtual boot address space.
Figure 19 Initial Boot Address Space VA=1000.0000 REGION 0 HWRPB Data Structure Console Service Routines Memory BITMAPS VA=2000.0000 REGION 1 Loaded System Software XX−No Access−XX SP: 1 page stack XX−No Access−XX VA=4000.
14.5.3 Halt The console (halt) program interprets commands entered at the console terminal and controls the operation of the main processor. Through the console terminal, an operator can boot the operating system, a field technician can maintain the system, and a system user can communicate with running programs. The processor can halt as the result of an operator command, a serious system error, a HALT instruction, or a boot failure.
Table 49 Processor Restart Codes Halt Code Description 0 Reserved 1 Powerup has occurred 2 Console operator halted system through halt command (ctrl-P) 3 Console operator requests a system crash 4 Processor executed HALT instruction in kernel mode 5 Processor halted due to Kernel-Stack-Not-Valid interrupt 6 Processor halted due to Double Error abort 7 Invalid SCBB 8 Invalid PTBR 9-FF Reserved Other Implementation-specific • Power On Console mode is entered at power on if the default
15 Configuration The power-up initialization code saves information about the devices in the configuration tables. The power-up initialization code sizes the system and builds a memory-resident configuration data structure, which is linked together as shown in Figure 20. The main configuration table (MCT) contains pointers to the device configuration tables (DCTs). This chapter covers the following topics: • Main configuration table (Section 15.1) • Device configuration tables (Section 15.
15.1 Main Configuration Table System ROM code loads the MCT into the diagnostic area of main memory, where it resides as long as power remains on. The system ROM main configuration code is initialized with all the devices that are part of the system kernel and includes six extra slots for potential TURBOchannel options. The DCTs associated with non-TURBOchannel options and a generic TURBOchannel DCT entry are resident as part of the system ROM code and are preinitialized once they are loaded to RAM.
The header components of the MCT are: Component Address Length Description Major version ID MCT 4 Bytes Tracks major changes in the diagnostic interface. Minor version ID MCT + 0416 4 Bytes Tracks minor changes in the diagnostic interface. Edit version ID MCT + 0816 4 Bytes Reserved. Number of devices in the system MCT + 0C16 4 Bytes Number of entries in the MCT table.
Figure 22 Kernel-Resident Device Configuration Table Major Version ID Minor Version ID Number of Directories Device ID Device Name TURBOchannel Slot Self Test Error Self Test FRU Code Address of Self Test Extended Status Address of Extended Configuration Address of Permanent Memory Directory Type Address Code Directory Type Address of Code MR−0147−93RAGS 15–4 Configuration
Table 50 Kernel-Resident Device Configuration Table Components Component Address Length Description Major version ID DCT 4 Bytes Tracks major changes in the device’s diagnostic routines. Minor version ID DCT + 0416 4 Bytes Tracks minor changes in the device’s diagnostic routines. Number of directories DCT + 0816 4 Bytes Gives the number of directory entries for this device. A directory entry lists the location of a particular component of code for this device.
Table 50 (Cont.) Kernel-Resident Device Configuration Table Components Component Address Length Description Pointer to allocated permanent memory DCT + 2C16 4 Bytes A pointer to the permanent memory that has been allocated. This field is filled in by the diagnostic the first time that it allocates memory. The diagnostic uses the same segment of memory for all subsequent invocations. The next two fields are replicated once for each directory entry that the device supports.
Figure 23 TURBOchannel Device Configuration Table Major Version ID Minor Version ID Number of Directories Device ID Device Name TURBOchannel Device Number Self Test Error Self Test FRU Code Address of Self Test Extended Status Address of Extended Configuration Address of Permanent Memory TURBOchannel Directory Type Slot 0 Address of TURBOchannel Directory Type Slot 0 TURBOchannel Directory Type Slot 5 Address of TURBOchannel Directory Type 5 MR−0148−93RAGS Configuration 15–7
Table 51 TURBOchannel Device Configuration Table Components Component Address Length Description Major version ID TC_DCT 4 Bytes Major version ID of this data structure: 1 for DEC 3000 AXP. Minor version ID TC_DCT + 416 4 Bytes Minor Version ID of this data structure: 0 for DEC 3000 AXP. Number of TURBOchannel option slots TC_DCT + 816 4 Bytes Number of TURBOchannel option slots in the system: up to 6 on the DEC 3000 AXP.
Table 52 (Cont.
16 Console This chapter covers the following topics: • Console device (Section 16.1) • Console saved state (Section 16.2) • Console program (Section 16.3) • Console commands (Section 16.4) • Console data structures (Section 16.5) • Console service routine overview (Section 16.6) • Console service routine descriptions (Section 16.7) 16.
16.1.1 Capabilities of Built-in Console Terminal: Keyboard The LK401 supports 16 national variations. The Console program supports main array keycode translations for the 16 types. The variation cannot be determined by querying the keyboard; instead, the user selects the desired keyboard layout at power-on either through a menu that appears at the first entry to the console program after NVR failure (see Figure 24) or through the SET LANG command.
The first glyph is the space character (2016 ), continuing through successive ASCII characters to the tilde character (7E16 ); these are followed by the characters A016 through FF16 in the DEC supplemental Character Set. There are glyphs for 95 ASCII characters and 96 DEC Supplemental characters in this table. Undefined characters are imaged as an error character (a backwards question mark). If the console device is a TURBOchannel option, it probably uses its own font.
16.2 Console Saved State Table 53 lists the saved information after console program entry.
16.3.2 Console Operation Special keys and signals are used by the console program: • Ctrl/U Ignores the current command line. The console prompt appears on the next line. This key sequence affects only the current line. The console program echoes this as ‘‘^U.’’ Pressing Ctrl/U while a command is executing does not abort the command. •
displayed on the console display, but are not included in the actual command line. • The command interpreter is case-insensitive. The lowercase ASCII characters ‘‘a-z’’ are treated as uppercase characters. • The parser rejects characters with codes greater than 7F16 , although these characters are acceptable in comments. • Type-ahead is not supported. Characters received before the Console prompt is displayed are checked for special characters ( Ctrl/S , Ctrl/Q , Ctrl/C ) but are otherwise discarded.
16.4 Console Commands The console program supports these commands: Command Description BOOT Initiates the bootstrap process. CONTINUE Returns operating system from console to program mode. DEPOSIT Writes to memory, I/O, and register locations. EXAMINE Displays specific memory, I/O, and register locations. HALT Halts the current program and places the system from program mode to console mode. HELP Displays basic help file. LOGIN Secures the system. REPEAT Repeats commands.
Parameters/Qualifiers device_name A device from which the firmware attempts to boot. Note A default boot devices may be specified by using the SET BOOTDEF_DEV command.
Example 3 Sample Boot Commands >>> boot -fl 0,0 esa0 !Performs a MOP boot to device ESA0 with the FLAGS = 0,0 >>> boot ! Performs a boot using the default boot specification >>> boot dka400 ! Performs a boot from device dka400 using the default flag values >>> boot "2/dka400" ! Performs a boot from TURBOchannel option slot number 2, device dka400 >>> boot "3/esa0" -fi "tmp/vmunix" ! Performs a network boot from a TURBOchannel option 16.4.
Options/Qualifiers access size options -b Byte data size -w Word data size -l Longword data size -q Quadword data size address options -pm The address space is physical memory. -vm The address space is virtual memory. All access and protection checking occur. If the access would not be allowed to a program running with the current PS, the console issues an error message. Virtual space DEPOSIT commands set the PTE M bit.
Note Exercise care when using this address function. The options that may be accepted apply to the current address while the options from the previous command is used for the indirect reference. Example 4 shows how the options are interpreted. Example 4 Indirect Addressing >>> DEPOSIT R0 200000 ! The value 200000 is stored directly in R0. >>> DEPOSIT -PM @R0 200000 ! ! ! ! The value 200000 is stored directly into the address pointed to by R0.
Table 55 lists supported mnemonic addresses. Table 55 Symbolic Addresses—General Symbol Description R General purpose registers (n = a decimal number 0 through 31) FR Floating point registers (n = a decimal number 0 through 31) SP Stack pointer PC Program counter PS Program status ASN Address space number ASTEN AST Enable ASTSR AST Summary AT Absolute time FEN Floating point enable IPIR Interprocessor interrupt request. Not implemented.
Example 5 Sample Deposit Commands ! This example deposits 01234567 into location 00400000 and five ! subsequent locations: >>> D -PM -N:5 400000 01234567 ! This example verifies the deposit operation >>> E -PM -N:5 400000 ! This is the result: PMEM: PMEM: PMEM: PMEM: PMEM: PMEM: 00000000.00400000 00000000.00400004 00000000.00400008 00000000.0040000C 00000000.00400010 00000000.
Example 5 (Cont.) Sample Deposit Commands ! This example deposits 0123456789ABCDEF into floating ! point registers 0-8.
After initialization, the default address space is physical memory, the default data size is a longword, and the default address is 0. If conflicting address space or data sizes are specified, the console ignores the command and issues an error message. Options/Qualifiers address access size options -b Byte data size -w Word data size -l Longword data size -q Quadword data size address options -pm The address space is physical memory. -vm The address space is virtual memory.
@ Indirect operation. Take the address specifier and use it as the pointer to the data. The format of the sequence is actually @address where address can be any other valid address value except another @. If no value is specified, address is treated as the previous address used in any other console command. Note Exercise care when using this address function. The options that may be accepted apply to the current address while the options from the previous command are used for the indirect reference.
Example 6 (Cont.) Sample Examine Commands PMEM: 00000000.01000000 00000000 00000000 >>> ! This example examines the next three memory address locations: >>> E -N:2 1000000 ! Result: PMEM: PMEM: PMEM: >>> 000000.01000000 00000000 00000000 000000.01000008 00000000 00000000 000000.01000010 00000000 00000000 ! This example examines physical memory. >>> E -PM 1000000 ! Result: PMEM: >>> 000000.01000000 00000000 00000000 ! This example examines the physical memory longword.
16.4.5 HALT The HALT command stops the execution of instructions and initiates console mode. >>> HA[LT] A message is displayed indicating that the processor has halted and displaying the contents of the program counter. If the processor was halted before the HALT command was issued, the command has no effect. Note Pressing the Halt button on the DEC 3000 AXP system performs the same function as the HALT command. Example 7 Sample Halt Commands >>>HA ?2E HLTED 16.4.
Example 8 Sample Help Command >>> HELP SHOW ! Result: PRINTENV | SHOW { AUTO_ACTION BOOT_RESET DIAG_LOE ENABLE_AUDIT FAST_SCSI_A LANGUAGE POWERUP_TIME SCSI_B SERVER >>> | | | | | | | | | BOOTDEF_DEV CONFIG DIAG_QUICK ETHERNET FAST_SCSI_B MEMORY RADIX SCSI_RESET TRIGGER} | | | | | | | | BOOT_OSFLAGS DEVICE DIAG_SECTION ERROR LANGUAGE MOP SCSI_A SECURE | | | | | | | | 16.4.8 LOGIN The LOGIN command enters the privileged state, if it has been enabled.
16.4.10 SET[ENV] The SETENV command sets the specified environment variable to the indicated value and displays the results of the setting. >>> SET[ENV] environment value [value] The output has the format: environment = value, where environment is the result of the SETENV entered at the console prompt. The SETENV PASSWORD command does not conform to this behavior for security reasons. This command requires that the name of the environment variable be explicitly entered.
The acceptable values are: • 0 (OFF) Do not reset 1 (ON) Reset the system DIAG_LOE If set, the diagnostic loops forever on a diagnostic failure. All output is suppressed and the user must press the external HALT button to return to console mode. This feature is available only with loadable diagnostics. • DIAG_QUICK This environment variable determines the diagnostic test mode by changing the way the startup diagnostics behave.
The FAST_SCSI_A and FAST_SCSI_B environment variables initialize the SCSI controllers. The variable FAST_SCSI_A is for bus A devices and FAST_ SCSI_B is for bus B devices. When the fast SCSI devices are connected and FAST_SCSI_A/B is set to on, the SCSI firmware will operate in fast SCSI mode. If both slow and fast SCSI devices are connected to the same bus and the FAST_SCSI_A/B environment variable is on, the firmware will differentiate between devices.
Set the default input radix to the specified value. Values that can be assigned to the default radix are: 0 DEFAULT Use the default radix for the associated command 10 DECIMAL Use decimal as the default radix. All data entered at the keyboard must be in decimal. 16 HEXADECIMAL Use hexadecimal as the default radix. All data must be entered as hexadecimal values. The default input radix can be changed at any time by the use of the %X and %D introducers. The results are always displayed in decimal.
For security reasons there is no corresponding SHOW command: the password is one-way encrypted and cannot be displayed. Section 16.4.15 describes the DEC 3000 AXP security system. This command behaves differently than the other SET commands. The parser does not accept the passwords on the command line. Instead, the user is prompted for the password data, and the system does not not echo the input. Example 9 shows the input sequence for a system that has a password already set.
Table 59 (Cont.) POWERUP_TIME Settings Name Description POWERUP_TIME = 3 or MAX Same as POWERUP_TIME = STD with some additional SCSI and NI testing. For SCSI: reads from all disk and tape devices. These tests require that tape drives have written media installed and that floppy drives have formatted media installed (preferably media that has been written to). If media is not present, not formatted (floppy), or not written to (tape), then an error will be reported. For NI: test for a network connection.
Example 10 Sample SHOW CONFIG Command >>> SHOW CONFIG DEC 3000 - M500 Digital Equipment Corporation VPP PAL X5.44-82000101/OSF PAL X1.32-82000201 - Built on 25-JUN-1994 09:52:26.46 TCINFO ------ DEVNAM -------CPU OSC ASIC MEM DEVSTAT -------OK KN15-AA - V3.0-S0F0-I080 - sV2.0 - DECchip 21064 P3.0 OK 150 MHz OK OK 8 CXT OK NVR SCC NI ISDN OK OK OK OK SCSI TC4 OK 7 6 4-PMAGB-BA Displays the current system configuration. Example 10 shows a sample SHOW CONFIG command and resulting display.
Looping on error is available on loadable diagnostics only. • DIAG_QUICK Displays the current state of quick-mode operation. If the value is OFF, normal operation of the testing is performed. If the value is ON, fast boot is selected and not all TURBOchannel diagnostics may be executed. • ENABLE_AUDIT Indicates if the boot audit-trail message generation is enabled. • ERRORS Displays the errors that occurred on the system the last time the self-test or system test was executed.
• LANGUAGE Shows the console keyboard type. The displayed values correspond to the language selection codes that are specified as part of the SET LANG command. If the system is not a workstation, this command is ignored.
Shows the state of the enable Network Listener bit and the data link counters associated with the network listener. If the value returned is OFF, the network listener is disabled; if the value returned is ON, the listener is enabled. This is displayed as: • 0 (off) MOP is disabled 1 (on) MOP is enabled POWERUP_TIME The POWERUP_TIME environment variable only affects powerup tests. If the TEST command is entered at the console, the tests will be run according to the setting of the DIAG_ENV.
• SERVER Displays the current value of the server environment variable. The variable is set to ON if the configuration is a server; otherwise it is set to OFF. • TRIGGER Shows the state of remote trigger enable. If the returned value is 0, remote triggers are not allowed. If the returned value is 1, remote triggers are allowed, provided that the remote trigger password is set correctly. 16.4.12 START The START command starts instruction execution at the specified address.
16.4.14 ! (COMMENT) Precedes a comment on a command line. >>> ! comment >>> command ! comment The system does not execute input following a comment character on the current line. 16.4.15 Console Security The console features a password mechanism that restricts the use of console commands that might compromise system security. Unsecured workstation consoles might allow unidentified users to boot and halt a system or to modify memory and continue privileged operation.
• The comment character (!), which allows only comments. 16.4.18 Forgotten Password If a user forgets the password, perform the following actions to recover: 1. Power off the machine. 2. Remove the security jumper from the I/O module, so that the console powers up to the privileged state. 3. Power up the machine. 4. Enter the following command at the console prompt to clear the password so the user can set a new password: >>> D -PM -U -N:2 1E0200088 0 ! ZERO OUT THE PASSWORD 5.
Figure 25 General HWRPB Structure General Information Per−CPU Slots (One CPU on DEC 3000) Console Terminal Block Console Routine Block Memory Data Descriptor Table MR−0149−93RAGS Console 16–33
16.5.1 HWRPB: General Information Portion Figure 26 shows the general information portion of the HWRPB, which contains general information about the system and information pointing to other HWRPB portions.
Figure 26 HWRPB General Information HWRPB Physical Address HWRPB HWRPB in ASCII +08 HWRPB Revision +10 HWRPB Size +18 Primary CPU ID +20 Page Size +28 Physical Address Size +30 Maximum Valid ASM +38 System Serial Number +40 System Type +50 System Variation +58 System Revision Code +60 Interval Clock Interrupt Frequency +68 Cycle Counter Frequency +70 VPTB_value +78 Reserved for Architecture Use +80 TBhint_offset +88 Number of Per-CPU Slots +90 Per-CPU Slot Size +98 Offs
The components of the general portion of the HWRPB are: 16–36 Console Component Address Length Description HWRPB physical address HWRPB 8 bytes The starting physical address of the HWRPB. HWRPB in ASCII HWRPB + 816 8 bytes Contains the ASCII string <0><0><0>. This field is used when validating an existing HWRPB. HWRPB revision HWRPB + 1016 8 bytes HWRPB version, which allows tracking of future changes to the HWRPB. HWRPB size HWRPB + 1816 8 bytes Size of HWRPB in bytes.
Component Address Length Description Number of per-CPU slots HWRPB + 9016 8 bytes The number of per-CPU slots in the HWRPB. This field contains 1. Per-CPU slot size HWRPB + 9816 8 bytes The size in bytes of the per-CPU slot rounded up to the next integer multiple of 128. This field contains 512. Offset to perCPU slot HWRPB + A016 8 bytes Unsigned offset from the starting address of the HWRPB; yields a quadword-aligned address that points to the first per-CPU slot in the HWRPB.
Component Address Length Description Restart routine virtual address HWRPB + 10016 8 bytes The starting virtual address of the CPU restart routine provided by the system software. The console initializes this field to 0. When the system software updates this field, it must recalculate the checksum of bytes 0016 -C816 of the HWRPB. Restart routine procedure value HWRPB + 10816 8 bytes The procedure value of the CPU restart routine provided by the system software.
Figure 27 HWRPB Per-CPU Slot SLOT Bootstrap / Restart HWPCB Per−CPU Slot State Bits +0 +80 PALcode Memory Space Length +88 PALcode Scratch Space Length +90 Physical Address of PALcode Memory Space +98 Physical Address of PALcode Scratch Space +A0 PALcode Revision +A8 Processor Type +B0 Processor Variation +B8 Processor Revision +C0 Processor Serial Number +C8 Logout Memory Address +D8 Logout Length +E0 Halt PCBB +E8 Halt PC +F0 Halt PS +F8 Halt Argument List +100 Halt Return
Component Address Length Description Bootstrap/Restart HWPCB +0 128 bytes The initial hardware privileged context block to be owned by the processor. Console initialization fills the fields of the HWPCB as shown.
Component Address Length Description Physical address of PALcode memory space + 98 8 bytes Starting physical address of the PALcode for this processor. Physical address of PALcode scratch space + A0 8 bytes Starting physical address of the PALcode scratch space. PALcode revision + A8 8 bytes The PALcode revision is broken up as shown in Figure 28. Processor type + B0 8 bytes Identifies the type of processor; field contains 2.
Component Address Length Description Halt procedure value + 110 8 bytes Value of R26 (procedure value) when a processor halt condition is encountered; this value is cleared to zero at system bootstraps or secondary processor starts. Reason for halt + 118 8 bytes The value which indicates why the processor was halted.
Alpha = an alphabetic character (a - z) 16.5.3 HWRPB: Console Terminal Block Portion The console terminal block (CTB) is the primary data structure that indicates which device is the current console terminal and describes its characteristics. The CTB is quadword-aligned; its starting address is an offset from the beginning of the HWRPB; the offset pointer is saved at HWRPB[B8].
Figure 29 Format of a Console Terminal Block (Decimal Values) 63 31 00 Console Type CTB Console Unit Number +08 Reserved +16 Length of the Device Dependent Information +24 Console Device IPL +32 Console Transmit Interrupt Vector +40 Console Receive Interrupt Vector +48 Console Terminal Type +56 Keyboard Type +64 Address of the Keyboard Translation Table +72 Address of the Keyboard Map Table +80 Keyboard State +88 Last Key Entered +96 Address of the US FONT Table +104 Address
Offset Component Description CTB Console type Console terminal device type. The device type is 04. CTB format 04 supports the following as legal console devices: a graphics device, a terminal or printer off the printer port, or the network. +08 Console unit number Unit number of the console. This applies only to console devices that support multiple units. The following table lists the supported console types on a DEC 3000 AXP.
16–46 Console Offset Component Description +16 Reserved This field is reserved as specified in the ALPHA SRM. +24 Length of the devicedependent information The length in bytes of the rest of the Console Terminal Block, as filled by the MACHINE RESET PALcode. +32 Console device IPL The IPL level at which the console interrupts. +40 Console transmit interrupt vector The interrupt vector for transmit interrupts, 80016 .
Offset Component Description +192 Opwindow up/down A flag used to determine whether the Opwindow is on the displayable screen on a graphics console. +200 Head offset The offset to the head-specific data. +208 TURBOchannel The graphics console port driver uses this to output a option character when the console device is a TURBOchannel option. PUTCHAR pointer +216 I/O state Flags to denote things such as CTRL-C, XON and XOFF states.
Figure 30 Format of a Console Routine Block 63 0 Virtual Address of DISPATCH Routine :CRB Physical Address of DISPATCH Routine +08 Virtual Address of FIXUP Routine +10 Physical Address of FIXUP Routine +18 Number of Entries in the Physical/Virtual Table +20 Number of Pages to be Mapped +28 Virtual Address of Console Service Routines +30 Physical Address of Console Service Routines +38 Size in Pages for Console Service Routines +40 Virtual Address of the Last Entry Physical Address of the
Component Address Length Description Virtual address of the DISPATCH routine CRB 8 bytes The virtual address of the procedure descriptor for the console service DISPATCH routine. The second quadword of a procedure descriptor contains the entry address of the procedure. The DISPATCH routine is the common routine that handles all console service routines.
16.5.5 HWRPB: Memory Data Descriptor Table Portion The memory data descriptor table (MEMDSC) contains a description of all physical memory found during memory sizing. The MEMDSC is quadwordaligned and begins at an offset from the beginning of the HWRPB (HWRPB[C8]). The data in the MEMDSC consists of memory cluster descriptors. The memory cluster descriptors are built for each contiguous chunk of memory that previous testing has found to be good.
Figure 31 Format of the Memory Data Descriptor Table C L U S T E R # 1 Checksum MEMDSC Physical Address of Optional Information +08 Number of Clusters +10 Starting PFN +18 Page Count +20 Tested Page Count +28 Virtual Address of Cluster Bitmap +30 Physical Address of Cluster Bitmap +38 Bitmap Checksum +40 Usage +48 Starting PFN Page Count C L U S T E R # n Tested Page Count Virtual Address of Cluster Bitmap Physical Address of Cluster Bitmap Bitmap Checksum Usage MR−0155−93RAGS Conso
Component Address Length Description Checksum MEMDSC 8 bytes A 64-bit 2’s complement sum (ignoring overflows) of all the quadwords in the memory data descriptor table, starting at the second quadword in the table. Physical address of optional information +8 8 bytes An implementation-dependent field. We may store the physical address of a table that contains all the bank configuration register values in the DEC 3000 AXP.
16.6 Console Service Routine Overview The console supplies console service routines that can be used by system software. These routines provide an architecturally consistent interface to the underlying hardware. The console routine block contains the interface to the console service routines. The FIXUP routine is called when system software needs to virtually relocate all the console routines and any data or I/O references used by the console service routine.
16.6.2 The DISPATCH Routine All console service routines, except the FIXUP routine, are dispatched through the DISPATCH routine. The DISPATCH routine is passed a hexadecimal function code and a variable argument list. The routines and their associated function codes are listed in the next table: Table 60 Service Routines accessed by the DISPATCH ROUTINE Code Function Description 0116 GETC Get a character from the console terminal. 0216 PUTS Put a string to the console terminal.
Table 61 (Cont.) Console Service Routines Routine Description GETENV Get an environment variable from the name space table. IOCTL Perform device specific i/o operations Unsupported through TURBOchannel options. OPEN Open an I/O device for access. PROCESS_ KEYCODE Translate a LK401 keycode into an ASCII character. PUTS Put string to console terminal. READ Read from an I/O device. RESETENV Resets an environment variable to its default state.
CLOSE CLOSE Close an I/O device to access. Format status = DISPATCH(CLOSE, channel_nbr); Arguments CLOSE CLOSE function code (1116 ). channel_nbr The channel number of the device to be closed. Description This routine closes a device to I/O access by deassigning the device’s channel number.
FIXUP FIXUP Readjust virtual address references internal to the console service routines. Format status = FIXUP (new_base_va, hwrpb_va); Arguments new_base_va The new starting virtual address for the console service routines and their I/O pages. hwrpb_va The new starting HWRPB virtual address. Description The FIXUP routine adjusts the virtual address references in the console service routines and their I/O pages, in the HWRPB, and in the current information of the map entries in the CRB.
GETC GETC Get a character from the console terminal. Format char = DISPATCH(GETC, UNIT); Arguments GETC The function code for GETC (116 ). UNIT The unit number from which to get the character. Section 16.5.3 gives unit number information. Description The GETC console service routine attempts to read one character from the current console device. If a character is available it is returned in the low 32 bits of R0. The character is echoed on the console terminal.
GETENV GETENV Get an environment variable from the name space table. Format status = DISPATCH(GETENV, env_id, buffer_ptr, buffer_length); Arguments GETENV GETENV function code (2216 ). env_id ID number of the environment variable. buffer_ptr Virtual address of the buffer to write the environment value. buffer_length Length of the buffer. Description This routine reads the environment variable from the name space table and saves it in the buffer pointed to by buffer_ptr.
IOCTL IOCTL Perform device-specific I/O operations; unsupported through TURBOchannel options. Format status = DISPATCH(IOCTL, channel_nbr, opt_p1, opt_p2, opt_p3, opt_p4); Arguments IOCTL IOCTL function code (1216 ). channel_nbr Channel associated with the device on which to perform the operation. opt_p1 Optional parameter 1.
IOCTL Returns: R0<63:62> = 00 R0<63:62> = 10 R0<63:62> = 11 R0<61:60> R0<59:32> R0<31:0> Success Failure, position not found Hardware failure Should be zero Device-dependent error status Number of skips performed Console 16–61
OPEN OPEN Open an I/O device for access. Format status = DISPATCH(OPEN, device_str, device_str_length); Arguments OPEN OPEN function code (1016 ). device_str Virtual address of a device name string.
OPEN Returns: R0<63:62> = 00 R0<63:62> = 10 R0<63:62> = 11 R0<61:60> R0<59:32> R0<31:0> Success Failure, device does not exist Failure, device can not be accessed or prepared Should be zero Device-specific error status Assigned channel number for this device Console 16–63
PROCESS_KEYCODE PROCESS_KEYCODE Translate a LK401 keycode into an ASCII character. Format status = DISPATCH(PROCESS_KEYCODE, unit, keycode, again); Arguments PROCESS_KEYCODE PROCESS_KEYCODE function code (0616 ). unit The console terminal unit number found in the CTB data structure. keycode The keycode to be translated. again This variable is 116 , if a call is made to translate the same keycode; otherwise, it is a 016 . Description PROCESS_KEYCODE translates the passed character to an ASCII character.
PUTS PUTS Put string to console terminal. Format count = DISPATCH(PUTS, unit, string_ptr, string_length); Arguments PUTS Put string function code (0216 ). unit Unit number of the device to write in a multiunit configuration; otherwise MBZ. Section 16.5.3 gives unit number information. string_ptr Virtual address of the byte string to write. string_length Number of bytes in the string. Description This routine attempts to output a byte string to the console terminal device.
READ READ Read from an I/O device. Format status = DISPATCH(READ, channel_nbr, byte_count, buffer_ptr, block); Arguments READ READ function code (1316 ). channel_nbr The channel number of the device to access. byte_count The number of bytes to read from the device. buffer_ptr The virtual address of the buffer into which the data is read. block The location from which to read the data on the device.
READ Returns: R0<63> = 0 R0<63> = 1 R0<62> = 1 R0<62> = 0 R0<61> = 1 R0<61> = 0 R0<60> = 1 R0<60> = 0 R0<59:32> R0<31:0> Success Failure END-OF-FILE condition encountered Otherwise Illegal record length specified Otherwise END-OF-TAPE encountered Otherwise Device-dependent status Number of bytes that were read Console 16–67
RESETENV RESETENV Resets an environment variable to its default state. Format status = DISPATCH(RESETENV, env_id, value_ptr, length); Arguments RESETENV RESETENV function code (2116 ). env_id ID number of the environment variable. value_ptr Starting virtual address of byte stream to contain the default value. length Number of bytes in the byte stream. Description This routine resets an environment variable associated with env_id to its default state.
RESET_TERM RESET_TERM Reset the console terminal to a default state. Format DISPATCH(RESET_TERM, UNIT); Arguments RESET_TERM RESET_TERM function code (0316 ). UNIT Unit number to reset (only unit 0 supported). Description This routine resets the console terminal to its default state. This action resets the line characteristics for a serial-line type device. This action resets the state of a graphics-type device, clears the screen, and homes the cursor to Row 0, Column 0.
SETENV SETENV Set an environment variable to the specified value. Format status = DISPATCH(SETENV, env_id, buffer_ptr, buffer_length); Arguments SETENV SETENV function code (2016 ). env_id ID number of the environment variable. buffer_ptr Virtual address of the byte stream containing the value. buffer_length Length of the byte stream. Description This routine causes the environment variable associated with env_id to have the value passed in by the user.
SETENV Table 62 (Cont.
SET_TERM_INTR SET_TERM_INTR Set the state of the console terminal interrupts. Format DISPATCH(SET_TERM_INTR, UNIT, int_mask); Arguments SET_TERM_INTR SET_TERM_INTR function code (0416 ). UNIT Unit number to set interrupts on. Section 16.5.3 gives unit number information.
TERMCTL TERMCTL Set up a new console terminal block. This routine is not currently supported on the DEC 3000 AXP. Format DISPATCH(TERMCTL, unit, new_ctb); Arguments TERMCTL TERMCTL function code (0516 ). unit Unit number of the device. new_ctb Virtual address of the new CTB. Description This routine changes the characteristics of the console terminal device. The changes are specified by the fields contained in a new CTB pointed to by new_ctb. The routine also changes the CTB.
WRITE WRITE Write to an I/O device. Format status = DISPATCH(WRITE, channel_nbr, byte_count, buffer_ptr, block); Arguments WRITE WRITE function code (1416 ). channel_nbr Channel number of the device to be written. byte_count The number of bytes to be written to the device. buffer_ptr Virtual address of the buffer from which to fetch the write data. block Logical block number of the data to be written. For disks, the physical block number; for FLASH ROMS, a section of the FLASH ROM.
WRITE Returns: R0<63> = 0 R0<63> = 1 R0<62> = 1 R0<62> = 0 R0<61> = 1 R0<61> = 0 R0<60> = 1 R0<60> = 0 R0<59:32> R0<31:0> Success Failure END-OF-TAPE or logical end of device encountered Otherwise Illegal record length specified Otherwise Run off end of tape Otherwise Device-dependent error status Number of bytes written Console 16–75
17 DEC 3000 AXP PALcode DEC 3000 AXP system Privileged Architecture Library code (PALcode) includes standard DECchip 21064 CPU PALcode in both its OpenVMS and DEC OSF/1 version and DEC 3000 AXP-specific PALcode.
Table 63 lists the PALcode entry points. Table 63 PALcode Entry Points Entry Name Offset Cause RESET 0000 Powerup or machine reset being performed. MCHK 0020 Uncorrectable hardware error. ARITH 0060 Arithmetic exception. INTERRUPT 00E0 Interrupt has occurred. DTB_MISS 09E0 DTB Miss has occurred. UNALIGN 11E0 Unaligned reference has occurred. DTB_FAULT 01E0 Remaining Dstream Memory management errors. ITB_MISS 03E0 ITB Miss has occurred.
Table 64 (Cont.
Table 64 (Cont.) Supported CALL_PAL Instructions Instruction Description MFPR Move from processor registers.
The PAL functions that include DEC 3000 AXP-specific code are: • MACHINE_RESET PALcode • MCHK—machine check PALcode • INTERRUPT—hardware interrupt PALcode • CFLUSH—flush a page from cache PALcode Refer to the Alpha Architecture Reference Manual for further information on standard PAL functions. 17.
IF a system machine check abort is pending (IRQ4) THEN check for interrupt bits set in the TC interrupt register IF one of the bits is set THEN Save the cause of the error Go build the machine check log vector to 660 ELSE dismiss the interrupt 17.5 INTERRUPT PALcode The INTERRUPT PALcode will be dispatched to when any correctable, uncorrectable, or I/O interrupt occurs in the DEC 3000 AXP.
18 TURBOchannel Support A MIPS emulator linked with a pseudo-REX environment is used to run TURBOchannel console, boot, and self-test routines. The system configures the TURBOchannel bus optional slots on powerup by finding a TURBOchannelformatted ROM in a slot. Table 65 gives the ROM base address for each option slot on the TURBOchannel.
19 Nonvolatile RAM The DEC 3000 AXP implements its nonvolatile RAM (NVR) using the RTC chip, as described in Section 9.5.2.7. The chip provides fifty bytes of NVR, each byte occupying bits <7:0> of 50 successive longwords. The SETENV console command sets the boot flags, boot device, halt action, and keyboard type. Note There is no checksum in the NVR. Table 66 maps the NVR Storage Allocation. Table 66 NVR Storage Allocation Address Dense I/O Space Name Description See 1.E020.
Table 66 (Cont.) NVR Storage Allocation Address Dense I/O Space Name Description See 1.E020.00C4-00FC BOOT_DEV Default boot device (15 bytes) Section 19.13 19.1 NVR Console Mailbox Register Figure 32 shows the NVR console mailbox register (CPMBX). Table 67 lists its fields. Figure 32 NVR Console Mailbox Register (CPMBX) 07 00 TRIG MOP HLT_SWX FAST_ SCSI_B FAST_ SCSI_A HLT_ACT MLO-012124 Table 67 NVR Console Mailbox Register Fields TRIG TRIGGER (bit <7>).
Table 67 (Cont.) NVR Console Mailbox Register Fields HLT_ACT Halt action (bits<1:0>) temporarily encodes the desired console action when the next internal processor halt occurs. The action taken is the same as that described for HLT_SWX. At power on, a restart halt action (HLT_ACT = 0 or 1) is treated as a boot request. This field is copied from the HLT_SWX field at power on and at entry to the console or when SET or SHOW HALT console commands are issued. 19.
19.3 NVR Keyboard Type Register Figure 34 shows the NVR keyboard type storage location. Figure 34 NVR Keyboard Type Register (LK401_ID) 00 07 LK401_ID MR−0158−93RAGS This field is ignored if an attached terminal is being used as the console device. Table 69 lists the language selection codes.
19.4 NVR Console Device Type Register Figure 35 shows the NVR console type storage location. Table 70 lists defined console devices. Figure 35 NVR Console Type Register (CONSOLE_ID) 00 07 CONSOLE_ID MR−0159−93RAGS This value indicates the console device type and is determined at power on. Note This field is determined at power on and cannot be relied upon to indicate the presence of hardware.
19.5 Temporary Storage (TEMP) Figure 36 shows the temporary storage location. Figure 36 NVR Temporary Storage (TEMP) 07 00 TEMP1<7:0> TEMP1<15:8> TEMP1<23:16> TEMP1<31:24> TEMP2<7:0> TEMP4<31:24> MR−0160−93RAGS These 11 bytes are reserved for use by the DEC 3000 AXP system firmware. 19.6 NVR Battery Check Data (BAT_CHK) Figure 37 shows the NVR battery check data storage location.
These four bytes are used by the firmware as an additional check on the NVR. These data are initialized to 5516 , AA16 , 3316 , 0F16 , when an NVR failure is detected at power on. 19.7 Ethernet Trigger Password Code (PASSWORD) Figure 38 shows the NVR Ethernet trigger password code (PASSWORD) storage location.
Table 71 (Cont.) NVR Security Flags POWERUP_ TIME POWERUP_TIME = 1 or MIN. Will only perform system initialization. Same as the INIT command. POWERUP_TIME = 2 or STD. The default setting of DEC 3000 AXP systems. POWERUP_TIME = 3 or MAX. Same as POWERUP_TIME = STD with some additional SCSI and NI testing. For SCSI: reads from all disk and tape devices.
The console stores the default boot flags in these 8 bytes, whose value is saved in an environment variable. The primary boot program fetches the boot flags from this environment variable. This field is zeroed on detection of an NVR failure at power on. It may be inspected and modified using the SHOW/SET BOOT_OSFLAGS console commands.
19.10 NVR SCSI Information 1 Figure 41 shows the SCSI information storage location. Table 72 lists the fields.
Table 73 (Cont.) NVR SCSI Information 2 Fields NI_P Ethernet port bit: 1 = 10BaseT; 0 = THICKwire FBOOT Fast boot; when set to 1, a fast powerup self-test mode is executed. 19.12 Default Boot Device Name Length (BOOT_DEV_LEN) Figure 43 shows the default boot device name length (BOOT_DEV_LEN) storage location. Figure 43 NVR Default Boot Device Name Length (BOOT_DEV_LEN) 00 07 BOOT_DEV LENGTH MR−0167−93RAGS This field contains the number of bytes in the default boot device name.
19.13 NVR Boot Device (BOOT_DEV) Figure 44 shows the boot device (BOOT_DEV) storage location. Figure 44 NVR Default Boot Device (BOOT_DEV) 07 00 BOOT_DEV0<7:0> BOOT_DEV1<7:0> BOOT_DEV2<7:0> BOOT_DEV3<7:0> BOOT_DEV4<7:0> BOOT_DEV14<7:0> MR−0168−93RAGS The console stores the boot device name in these 15 bytes. The name is stored as up to 15 alphanumeric ASCII characters, padded to the right with 0s as necessary.
A Dense and Sparse Space I/O space is divided into 8 512-MB slots corresponding to I/O ports and further divided into dense and sparse space. Caution: Dense and Sparse Space Interaction If operations that address the same location switch between dense and sparse space, you must execute memory barriers before changing spaces. Memory barriers prevent out-of-order accesses to those locations. Every byte of I/O space is doubly-mapped to a byte in dense I/O space and a longword in sparse I/O space.
A.1 Layout of Dense and Sparse I/O Space In dense I/O space, addresses increment conventionally, as shown in Figure 45 and Figure 46. In sparse I/O space, I/O locations reside in the even-numbered longwords and byte masks reside in the low 4 bits of the odd-numbered longwords, as shown in Figure 47 and Figure 48.
Figure 47 Sparse I/O Space Addressing: 400/500/600/700/800/900 Models Longword Locations (Each Row= One System Bus Cycle) Sparse I/O Byte PA BYTE MASK 4 ADDRESS 4 BYTE MASK 0 ADDRESS 0 :0 BYTE MASK C ADDRESS C BYTE MASK 8 ADDRESS 8 : 10 MR−0112−93RAGS Figure 48 Sparse I/O Space Addressing: 300 Models Longword Locations (Each Row = One System Bus Cycle) Sparse I/O Byte PA BYTE MASK 0 ADDRESS 0 :0 BYTE MASK 4 ADDRESS 4 :8 BYTE MASK 8 ADDRESS 8 : 10 BYTE MASK C ADDRESS C : 18 MR−0113
A.2 Required Number of Transactions The number of required system bus transactions to complete a read operation in dense I/O space differs from the required number in sparse I/O space. Depending on how you write the operating system and device drivers, you may incur more software overhead by formatting data for sparse I/O space read and write operations than by formatting them for dense I/O space write operations.
3. Clear byte-mask-enable bit in SSR in IOCTL to disable byte-masking of future I/O Reads. A.5 Effect of Load and Store Instructions in Dense and Sparse Space Table 75 lists the effect of load and store instructions in dense I/O space; Table 76 lists the effect of load and store instructions in sparse I/O space. Table 75 Effect of Load and Store Instructions in Dense Space Instr.
A.6.1 Performing Read and Write Operations You can perform block-mode write operations through the TURBOchannel bus only in dense I/O space. When you write to a number of I/O registers, the CPU attempts to gather them in 32-byte blocks, unless you instruct it otherwise with barrier instructions. Table 77 lists the effects of writing these chunks of data to the TURBOchannel interface.
Table 78 summarizes how to perform each operation referencing an I/O register. Table 78 How to Address I/O Registers Operation Steps to Perform Read 1-3 bytes from a register. Disable interrupts and exceptions; the IOSLOT register is a shared resource. Load the valid and byte mask bits into the IOSLOT register at its alternate address (see Section 3.3.1) Issue an LDL command to the register in its sparse I/O space location. Clear the Valid and Byte Mask bits in the IOSLOT register.
Address Mapping in Sparse I/O Space: The user shifts bits <26:2> to <27:3>, sets bit <28>, and manipulates bit <2> accordingly.
Glossary The glossary defines some of the technical terms and abbreviations used in this manual. ~ Indicates a negation in logic. A-box Component of the DECchip 21064 CPU that contains the following major sections: address translation data path, load silo, write buffer, data cache interface, external bus interface, and internal processor registers. ABOX_CTL register The A-box control register directs the actions of the DECchip 21064 CPU’s A-box unit. ASIC Application-specific integrated circuit.
Device configuation table A data structure containing extended information about each device connected to the system. The DEC 3000 AXP contains are two DCTs—the kernel-resident device configuration table, which lists information about devices that are part of the kernel, and the TURBOchannel device configuration table, which lists information about the TURBOchannel options that may be present in one of the six possible option slots.
Machine check An operating system action triggered by certain system hardware-detected errors that can be fatal to system operation. Once triggered, machine-check handler software analyzes the error. Masked write A write cycle that updates only a subset of a data block Main configuration table A data structure containing a list of the devices in the system and a pointer to the device configuration table corresponding to each device. Loaded by system ROM at initialization. MCT See main configuration table.
REX ROM executive. ROM Read-only memory. RTC The system’s real-time clock. It provides a system clock, battery-backed-up time-of-year clock, and battery-backed-up nonvolatile RAM (NVR) for use as system startup configuration parameters. SBCDBB Single-bit correction, double bit detection. SCC Serial communications controller SCSI Small computer system interface. An ANSI-standard interface for connecting disks and other peripheral devices to computer systems.
Index *, 16–10 +, 16–10 -, 16–10 -b, 16–10 -fi, 16–8 -fl, 16–8 -l, 16–10 -n, 16–10 -pm, 16–10 -q, 16–10 -s, 16–10 -u, 16–10 -vm, 16–10 -w, 16–10 @, 16–10 A ABOX_CTL, see ABOX control register Aborting transactions on dual SCSI, 9–19 ABOX control register, 2–9 to 2–10 fields, 2–10 format and settings in 300 models, 2–9 format and settings in 400/500/600/700/800/900 models, 2–9 300 models figure, 2–9 400/500/600/700/800/900 models figure, 2–10 Address ASIC memory configuration registers (400/500/600 /700/800
53CF94-2 (cont’d) unaligned DMA write operation, 9–19 CLEAR_INTERRUPT register, SFB ASIC, 6–16 Clock conversion factor register, NCR 53CF94-2, 9–17 CLOSE, console service routine, 16–56 Color map RAMDAC control registers, 6–20 updating, 6–23 Communication port 1 receive DMA pointer, 7–7 transmit DMA pointer, 7–7 Configuration tables, figure, 15–1 Conflicts, I/O, 9–7 Console commands, 16–7 to 16–32 list, 16–7 data structures, 16–32 to 16–52 HWRPB, 16–34 to 16–38 HWRPB console routine block, 16–47 HWRPB conso
DMA (cont’d) virtual programming requirements, 9–3 reading and writing scatter/gather map, 5–3 scatter/gather map format, 5–2 to 5–3 Dual SCSI aborting transactions, 9–19 address map, 8–2 ASIC required reconfiguration, 9–15 determining oscillator frequency, 9–16 differences among models, 9–15 DMA buffers, 8–14 error/interrupt matrix, 10–12 to 10–13 initiation of DMA transfers, 9–18 to 9–19 internal registers, 8–3 to 8–11 interrupt service, 9–19 unaligned DMA write operation, 9–19 Firmware system firmware e
I/O masked read operations (cont’d) 400/500/600/700/800/900 models, 9–7 memory configuration register 300 models, 3–5 to 3–6 read and write restrictions, 9–2 slot configuration register 400/500/600/700/800/900 models, 3–10 to 3–11 timeout, 9–6 TURBOchannel control and status register 300 models, 3–4 Initial boot address space, figure, 14–10 Initialization Bcache, 11–3 flow at power on, 14–1 to 14–5 processor, 11–1 to 11–3 power-on reset, 11–2 SROM sequence, 11–2 SYSROM sequence, 11–2 INITIALIZE console comm
Masked read operations 300 models, 9–7 400/500/600/700/800/900 models, 9–7 Memory address spaces, 2–2 alignment, 2–2 banks size and MCR, 4–3 configuration register 300 models, 3–5 to 3–6 configuring memory, 3–5 to 3–6 format, 3–5 use and format, 3–5 configuration registers boot time, 4–3 to 4–4 fields, 4–5 format and operation, 4–2 to 4–3 improper configuration, 4–4 reading and writing, 4–4 to 4–5 TURBOchannel interface 400/500/600/700/800/900 models, 4–2 to 4–5 writing with maximum memory size, 4–3 configu
P PAL entry point priority, 10–4 PALcode entering, 17–1 to 17–2 entry points list, 17–2 INTERRUPT, 17–6 machine check, 17–5 to 17–6 MACHINE_RESET, 17–5 overview, 12–4 revision quadword, figure, 16–42 supported CALL_PAL instructions, 17–2 to 17–5 PASSWORD keyword, 16–23 Physical address, CPU-generated, 2–7 to 2–8 Physical DMA, programming requirements, 9–3 Pins, interrupt, 10–15 PixelMask register, SFB ASIC, 6–14 PixelShift register, SFB ASIC, 6–15 Planemask register, SFB ASIC, 6–12 Power on initialization c
SETENV, console service routine, 16–70 SET_TERM_INTR, console service routine, 16–72 SFB ASIC, 6–7 to 6–19 SHOWENV console command, 16–25 Simple frame buffer mode, 6–9 Sparse I/O space address mapping, A–8 addressing in 300 models, figure, A–3 addressing in 400/500/600/700/800/900 models, figure, A–3 Sparse/dense space byte-masked I/O read operation, A–4 to A–5 layout, A–2 to A–3 load and store instructions, A–5 performing read and write operations, A–6 to A–8 read/write minimum granularity, A–4 required nu
V VACR, see victim address counter register VAR, see victim address register Vertical timing parameters register, SFB ASIC video timing registers, 6–18 Victim address counter, 4–6 to 4–7 counter register, 4–6 reading, 4–6 writing, 4–6 register, 4–6 to 4–7 VIDCLK_COUNT register, SFB ASIC counter clocks, 6–19 Index–8 Video base address register, SFB ASIC video timing registers, 6–17 refresh counter register, SFB ASIC video timing registers, 6–17 register map, 6–5 to 6–6 timing registers, SFB ASIC, 6–16 to 6
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