User`s guide

Address
Hex
o
1
2
3
4
5
6
13: 1 0
20
IFF: 100
Table A-2 Machine-Dependent Internal Registers
Dec
o
1
2
3
4
5
6
19: 16
32
511 :256
Register Mapping
Processor Status Longword
CPU Microprogram Counter (UPC)
Memory Controller CSR 1 Register
Memory Controller
CSR 2 Register
Set Breakpoint @ Microaddress
Enable/Disable
WCS Control Store Parity
WCS Control Store Register
CPU Scratch Pad Memory (WR3:WRO)
CPU Quotient Register
CPU Scratch Pad Memory (Local Store)
A-2