User`s guide

MACRO Support for 64-Bit Addressing
5.3 Declaring 64-Bit Arguments
QUAD_ARGS also affects the code generated for deferred mode operands that are
AP-based. If the effective address must be loaded from an argument in memory,
it will be read as a quadword, rather than a longword, if QUAD_ARGS is in
effect.
Keep these points in mind when using QUAD_ARGS:
• AP-based quadword argument-list references look strange because they
appear to overlap. You can improve this situation by defining symbolic names
for the argument-list offsets, for example, FIRST_ARG, SECOND_ARG, and
so forth. Users are encouraged to define meaningful symbolic names that
describe the uses of the arguments to make the source code more readable.
Alternatively, you can still use direct argument register references to refer to
the first six arguments on an OpenVMS Alpha system. (There is no access
to argument registers on OpenVMS I64.) Either way, it is useful to declare
QUAD_ARGS to ensure that the argument list is not homed.
• Routines that share code must have the same setting for QUAD_ARGS. If
they do not, the compiler will report a warning message.
• JSB routines cannot refer to their caller’s argument list if the caller has
QUAD_ARGS. References to AP within JSB routines require that the last
CALL_ENTRY have its argument list homed. HOME_ARGS and QUAD_
ARGS are mutually exclusive.
• QUAD_ARGS causes the $ARGn symbols, which the compiler places in the
debug symbol table, to be defined as quadwords rather than longwords. These
symbols allow easy access to received argument values and can be used in
place of register numbers or stack offsets when debugging with the symbolic
debugger.
5.4 Specifying 64-Bit Address Arithmetic
There are no explicit pointer-type declarations in MACRO. You can create a
64-bit pointer value in a register in a variety of ways. The most common are the
EVAX_LDQ built-in for loading an address stored in memory and the MOVAx for
getting the address of the specified operand.
After a 64-bit pointer value is in a register, an ordinary instruction will access
the 64-bit address. The amount of data read from that address depends on the
instruction used. Consider the following example:
MOVL 4(R1), R0
The MOVL instruction reads the longword at offset 4 from R1, regardless of
whether R1 contains a 32- or 64-bit pointer.
However, certain addressing modes require the generation of arithmetic
instructions to compute the effective address. For VAX compatibility, the
compiler computes these as longword operations. For example,
4 + <1@33> yields
the value 4 because the shifted value exceeds 32 bits. If quadword mode is
enabled, the upper bit will not be lost.
In compilers shipping with versions of OpenVMS Alpha prior to Version
7.0, the /ENABLE=QUADWORD qualifier (and the corresponding .ENABLE
QUADWORD and .DISABLE QUADWORD directives) only affected the mode
in which constant expression evaluations were performed. For OpenVMS Alpha
Version 7.0 and OpenVMS I64, these have been extended to affect address
MACRO Support for 64-Bit Addressing 5–5