User`s guide

MACRO Support for 64-Bit Addressing
5.4 Specifying 64-Bit Address Arithmetic
computations. They will result in addresses being computed with quadword
instructions, such as SxADDQ and ADDQ.
To have quadword operations used throughout a module, specify
/ENABLE=QUADWORD on the command line. If you want quadword operations
applied only to certain sections, use the .ENABLE QUADWORD and .DISABLE
QUADWORD directives to enclose those sections.
There is no performance penalty when using /ENABLE=QUADWORD.
5.4.1 Dependence on Wrapping Behavior of Longword Operations
The compiler cannot use quadword arithmetic for all addressing computations
because existing code may rely on the wrapping behavior of the 32-bit operations.
That is, code may perform addressing operations that actually overflow 32 bits,
knowing that the upper bits are discarded. Doing the calculation in quadword
mode causes an incompatibility.
Before using /ENABLE to set quadword evaluation for an entire module, check
the existing code for dependence on longword wrapping. There is no simple way
to do this, but as a programming technique, it should be rarely used and called
out by comments in the code.
The following Alpha example shows the wrapping problem:
MOVAL (R1)[R0], R2
Suppose R1 contains the value 7FFFFFFF and R0 contains 1. The MOVAL
instruction generates an S4ADDL instruction. The shift and add result exceeds
32 bits, but the stored result is the low 32 bits, sign-extended.
If quadword arithmetic were used (S4ADDQ), the true quadword value would
result, as shown in the following example:
S4ADDL R0, R1, R2 => FFFFFFFF 80000003
S4ADDQ R0, R1, R2 => 00000000 80000003
The wrapping problem is not limited to indexed-mode addressing. Consider the
following example:
MOVAB offset(R1), R0
If the symbol offset is not a compile-time constant, this instruction causes a value
to be read from the linkage section and added (using an ADDL instruction) to the
value in R1. Changing this to ADDQ may change the result if the value exceeds
32 bits.
The Itanium architecture does not have an equivalent of the S4ADDL instruction,
but the compiler generates a shladd instruction and an sxt4 instruction to
simulate the effect.
5.5 Sign-Extending and Checking
A built-in, EVAX_SEXTL (sign-extend longword), is available for sign-extending
the low 32 bits of a 64-bit value into a destination. This built-in makes explicit
the sign extension of the low longword of the source into the destination.
EVAX_SEXTL takes the low 32 bits of the 64-bit value, fills the upper 32 bits
with the sign extension (whatever is in bit 31 of the value) and writes the 64-bit
result to the destination.
5–6 MACRO Support for 64-Bit Addressing