User`s guide

MACRO Compiler Built-ins
C.1 Alpha Instruction Built-ins for OpenVMS Alpha and OpenVMS I64 Systems
%SYSTEM-F-OPCDEC, opcode reserved to Digital fault at
PC=00000000000020068,PS=0000001B
Note
Memory references in the MACRO compiler built-ins are always assumed
to be quadword aligned except in EVAX_SEXTB, EVAX_SEXTW, EVAX_
LDBU, EVAX_LDWU, EVAX_STB, EVAX_STW, EVAX_LDQU, and EVAX_
STQU.
Table C–1 summarizes the Alpha built-ins supported by the compiler. The
built-ins that are Alpha only (cannot be used to generate or access Itanium
instructions) are noted in the table.
Table C–1 Alpha Instruction Built-ins for OpenVMS Alpha and OpenVMS I64 Systems
Built-in Operands Description
Functional on
OpenVMS I64?
EVAX_SEXTB <RQ,WB> Sign-extend byte Yes
EVAX_SEXTW <RQ,WW> Sign-extend word Yes
EVAX_SEXTL <RQ,WL> Sign-extend longword Yes
EVAX_LDBU <WQ,AB> Load zero-extended byte from memory Yes
EVAX_LDWU <WQ,AQ> Load zero-extended word from memory Yes
EVAX_LDLL <WL,AL> Load longword locked Yes
EVAX_LDAQ <WQ,AQ> Load address of quadword Yes
EVAX_LDQ <WQ,AQ> Load quadword Yes
EVAX_LDQL <WQ,AQ> Load quadword locked Yes
EVAX_LDQU <WQ,AQ> Load unaligned quadword Yes
EVAX_STB <RQ,AB> Store byte from register to memory Yes
EVAX_STW <RQ,AW> Store word from register to memory Yes
EVAX_STLC <ML,AL> Store longword conditional Yes
EVAX_STQ <RQ,AQ> Store quadword Yes
EVAX_STQC <MQ,AQ> Store quadword conditional Yes
EVAX_STQU <RQ,AQ> Store unaligned quadword Yes
EVAX_ADDQ <RQ,RQ,WQ> Quadword add Yes
EVAX_SUBQ <RQ,RQ,WQ> Quadword subtract Yes
EVAX_MULQ <RQ,RQ,WQ> Quadword multiply Yes
EVAX_UMULH <RQ,RQ,WQ> Unsigned quadword multiply high Yes
EVAX_AND <RQ,RQ,WQ> Logical product Yes
EVAX_OR <RQ,RQ,WQ> Logical sum Yes
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MACRO Compiler Built-ins C–3