User`s guide

How the MACRO Compiler Functions on Different Platforms
2.11 Preserving VAX Atomicity and Granularity
.
fail: BR Retry
Note that the first BIC instruction uses #^B0110, not #^B0111. This is to ensure
that the word does not cross a quadword boundary, which would result in an
incomplete memory update. If the address in R1 is not pointing to an aligned
word, bit 0 will be set and the bit will not be cleared by the BIC instruction. The
Load Quadword Locked instruction (LDQ_L) will then generate a fatal reserved
operand fault.
An INCB instruction uses #^B0111 to generate the aligned address since all bytes
are aligned.
For the
INCW (R1) instruction, the compiler generates a code sequence such as the
following on OpenVMS I64 systems:
$L5: ld2 r19 = [r9]
mov.m apccv = r19
mov r18 = r19
sxt2 r19 = r19
adds r19 = 1, r19
cmpxchg2.acq r19, [r9] = r19
cmp.eq pr0, pr8 = r18, r19
(pr8) br.cond.dpnt.few $L5
2.11.6 Interlocked Instructions and Atomicity
The compiler’s methods of preserving atomicity have an interesting side effect in
compiled VAX MACRO code.
On OpenVMS VAX systems, only the interlocked instructions will work correctly
to synchronize access to shared data in multiprocessor systems. On OpenVMS
Alpha multiprocessing systems, the code resulting from a compilation of modify
instructions (with atomicity preserved) and interlocked instructions would both
work correctly, because the LDx_L and STx_C which the compiler generates for
both sets of instructions operate correctly across multiple processors. Likewise,
on OpenVMS I64 systems, the the compare-exchange (cmpxchg) instruction
provides interlocking across processors.
Because this compiler side effect is specific to OpenVMS Alpha and OpenVMS
I64 systems and does not port back to OpenVMS VAX systems, you should avoid
relying on it when porting VAX MACRO code to OpenVMS Alpha or OpenVMS
I64 if you intend to run the code on both systems.
However, interlocked instructions must still be used if the memory modification
is being used as an interlock for other instructions for which atomicity is not
preserved. This is because the Alpha and and Itanium architectures do not
guarantee strict write ordering.
For example, consider the following VAX MACRO code sequence:
.PRESERVE ATOMICITY
INCL (R1)
.NOPRESERVE ATOMICITY
MOVL (R2),R3
This code sequence will generate the following Alpha code sequence:
How the MACRO Compiler Functions on Different Platforms 2–29