User`s guide

How the MACRO Compiler Functions on Different Platforms
2.11 Preserving VAX Atomicity and Granularity
Retry: LDL_L R28,(R1)
ADDL R28,#1,R28
STL_C R28,(R1)
BEQ R28, fail
LDL R3, (R2)
.
.
.
fail: BR Retry
Because of the data prefetching of the Alpha and Itanium architectures, the data
from (R2) may be read before the store to (R1) is processed. If the INCL (R1)
instruction is being used as a lock to prevent the data at (R2) from being accessed
before the lock is set, the read of (R2) may occur before the increment of (R1) and
thus is not protected.
The VAX interlocked instructions generate Alpha MB (memory barrier) or
Itanium mf (memory fence) instructions before and after the interlocked sequence.
This prevents memory loads from being moved across the interlocked instruction.
On OpenVMS I64, the code sequence would be similar to the following:
$L7: ld4 r16 = [r9]
mov.m apccv = r16
mov r15 = r16
sxt4 r16 = r16
adds r16 = 1, r16
cmpxchg4.acq r16, [r9] = r16
cmp.eq pr0, pr10 = r15, r16
(pr10) br.cond.dpnt.few $L7
ld4 r3 = [r28]
sxt4 r3 = r3
Consider the following code sequence:
ADAWI #1,(R1)
MOVL (R2),R3
This code sequence will generate the following Alpha code sequence:
MB
Retry: LDL_L R28,(R1)
ADDL R28,#1,R28
STL_C R28,(R1)
BEQ R28, Fail
MB
LDL R3, (R2)
.
.
.
Fail: BR Retry
On OpenVMS I64, a code sequence similar to the following would be generated:
mf
$L8: ld2 r23 = [r9]
mov.m apccv = r23
adds r24 = 1, r23
cmpxchg2.acq r14, [r9] = r24
cmp.eq pr0, pr11 = r23, r14
(pr11) br.cond.dpnt.few $L8
mf
ld4 r3 = [r28]
sxt4 r3 = r3
2–30 How the MACRO Compiler Functions on Different Platforms