User`s guide

Recommended and Required Source Changes
3.2 Instruction Stream
Recommended Change
These instructions usually appear in code that is highly dependent on the VAX
architecture. You will need to rewrite such code to port it to OpenVMS Alpha or
OpenVMS I64 systems.
3.2.6 References to Internal Processor Registers
Pay special attention to the following instructions:
• MFPR
• MTPR
Recommended Change
On OpenVMS Alpha systems, verify that these instructions reference valid Alpha
internal processor registers (IPRs). If they do not, they will be flagged. For
more information about the Alpha internal processor registers, see the Alpha
Architecture Reference Manual.
On OpenVMS I64 systems, the compiler does not directly support the MFPR and
MTPR VAX instructions. On those systems, there is a set of OpenVMS-supplied
macros that result in calls to system services that perform the same function.
3.2.7 Use of Z and N Condition Codes with the BICPSW Instruction
The BICPSW instruction is supported, but the Z and N condition codes cannot be
set at the same time. Setting the Z condition code will clear the N condition code
and vice versa.
Recommended Change
If you find that your code sets both condition codes at the same time, modify the
code.
3.2.8 Interlocked Memory Instructions
The Alpha Architecture Reference Manual describes strict rules for using
interlocked memory instructions. In particular, branches within or into
LDxL/STxC sequences are not allowed. Branches out of interlocked sequences are
valid and need not change. The Alpha 21264 (EV6) processor and all subsequent
Alpha processors are more stringent than their predecessors in their requirement
that these rules be followed. The Alpha 21264 processor was first supported by
OpenVMS Alpha Version 7.1-2.
The MACRO compiler observes these rules in the code it generates from Macro-
32 source code. However, the compiler provides EVAX_LQxL and EVAX_STxC
built-ins which enable programmers to write these instructions directly in source
code.
To help ensure that these instructions are used in conformance with the rules
for using interlocked memory instructions, additional checking was added to the
MACRO compiler, starting in Version 3.1 of the compiler for OpenVMS Alpha
Version 7.1-2 and in Version 4.1 for OpenVMS Alpha Version 7.2.
On OpenVMS I64 systems, the compiler turns EVAX_LDxL built-ins into
instructions that also store the loaded value into the hardware AR.CCV register
as well as keep another local copy to use later. The compiler turns the EVAX_
STxC built-ins into a compare-exchange (cmpxchg) instruction that compares the
value previously saved by the EVAX_LDxL built-in. The compiler implements all
the Alpha rules about branching into an interlocked instruction sequence.
Recommended and Required Source Changes 3–5