User`s guide

Improving the Performance of Ported Code

This chapter describes how you can improve the performance of your ported code.

This chapter contains the following topics:

• Section 4.1, Aligning Data

• Section 4.2, Code Flow and Branch Prediction

• Section 4.3, Code Optimization

• Section 4.4, Common-Based Referencing

4.1 Aligning Data

An unaligned data reference will work but will be slow on OpenVMS Alpha

or OpenVMS I64, because the system must take an unaligned address fault

to complete the unaligned reference. If it is known that a data reference is

unaligned, the compiler can generate unaligned quadword loads and masks to

manually extract the data. This is slower than an aligned load but much faster

than taking an alignment fault. Global data labels that are not longword or

quadword aligned are ﬂagged with information-level messages.

In addition, unaligned memory modiﬁcation references cannot be made atomic

with /PRESERVE=ATOMICITY or .PRESERVE ATOMICITY. If this is attempted,

it will cause a fatal reserved operand fault.

4.1.1 Alignment Assumptions

By default, the compiler assumes the following:

• Addresses in registers used as base pointers are longword aligned at routine

entry.

• External references are longword aligned.

• Addresses that resulted from certain types of instructions, such as DIVL, are

assumed unaligned.

Every time a register is changed, the compiler determines whether the base

address in the register is still aligned. If the register and speciﬁed offset result

in an aligned address, the compiler uses an aligned load or store for a memory

reference. The compiler attempts to track register usage in terms of whether

the base address remains aligned. When a stored memory address is loaded, for

instance, MOVL 4(R1),R0, or used indirectly for instance, MOVL @4(R1),R0, the

compiler assumes the resulting address is aligned.

For quadword memory references such as MOVQ instructions, the compiler

assumes the base address is quadword aligned, unless it has determined by

means of its register tracking code that the address may not be longword aligned.

In other words, quadword register alignment is not tracked—only longword

alignment.

Improving the Performance of Ported Code 4–1