Technical data

Index
Instruction (Cont.)
issue time • 3–16
overlap • 1–8, 1–18, 2–5
Integrated vector processor • 1–7
Invalidate queue • 2–16
L
LAPACK library • A–5
Linpack • A–2
Load instruction • 3–15
Load/store
instruction • 2–7, 3–13
pipeline • 2–18
unit • 2–7, 2–11, 2–16, 2–18, 2–21, 3–11 to
3–15
Locality of reference of data • 3–17
Longword • 2–6, 3–13
Loop unrolling • A–5
M
Mask
operate enable (MOE) • 3–13
register • 3–15
Masked memory instruction • 3–15
Matrix
multiplication • 3–23, A–5
transpose • A–11
Maximize instruction overlap • A–1
Memory management • 2–11
exception • 2–14
exceptions • 3–8
fault • 3–11
fault priorites • 2–12
Memory management exceptions • 3–10
Memory Management Okay (MMOK) • 2–19,
3–14
Memory-to-memory architecture • 1–8
MFLOPS • 1–19
MIPS • 1–19
Modify intent bit (MI) • 3–13
Move From Vector Processor (MFVP)
instruction • 3–6
N
Nonunity stride • 3–18
O
Offset • 1–17
vector register • 3–15
Overhead • 1–22
Overlap • 1–8, 1–13, 1–18, 2–20, 2–21, 3–15
Overlapping instructions • 3–15
P
Page table entry • 2–11
Parallel pipelines • 1–13
Parity
bit • 2–15
errors • 2–8
Peak MFLOPS • 1–19
Performance • 1–2, 1–3, 1–7 to 1–9, 1–11,
1–19, 1–21, 1–22
Pipe • 1–11
Pipeline • 1–18, 2–5, 2–17, 2–18, 2–21, 3–21
latency • 1–12, 1–13
Pipelining • 1–11, 1–13
Precise exceptions • 3–11
Program counter (PC) • 3–10
Q
Quadword • 2–6, 2–14
R
Register
conflict • 3–12, 3–15, 3–17
file chip • 2–4 to 2–7, 2–9
offsets • 2–7
reuse • 3–25
Register length • 1–14
Register reuse • A–1, A–9
Register-to-register architecture • 1–8
Index–2