Technical data

Index
Return from Exception or Interrupt (REI)
instruction • 3–7
S
Scalar/vector memory synchronization • 3–7 to
3–9
Scalar/vector synchronization • 3–6
Scatter • 1–15, 1–17, 2–19
Scatter instruction • 3–13, 3–14, A–7
Scoreboarding • 2–5, 2–18
Sectioning • 1–14
SIMD • 1–3
Single-precision • 2–6
Speedup ratio • 1–22
Store operation • 3–13
Stride • 1–15, 3–13
Stripmining • 1–14
Subvector • 1–14
Synchronization • 3–6
Synchronize Vector Memory Access (VSYNC)
instruction • 3–9
SYNC instruction • 3–6
T
Translation buffer • A–4
Translation buffer (TB) • 2–7, 2–12, 2–14, 3–22
Translation-Not-Valid fault • 2–11
Trigonometric functions • A–8
Two-dimensional fast Fourier transforms • A–10
U
Unity stride • 1–15, 3–18, 3–22, A–1
Unknown dependency • 1–9
V
VAX instruction set • 2–2
Vector • 1–2
Arithmetic Exception Register • 2–5
cache • 3–21
control unit • 2–5, 2–9
Vector (Cont.)
Count Register • 2–5, 2–9
issue unit • 2–17, 2–19
length • 1–9, 3–21
Length Register • 1–9, 2–5, 2–9
Length Register (VLR) • 3–13
Mask Register • 1–9, 2–9
Mask Register (VMR) • 3–13
Memory Activity Check Register • 2–5
Processor Status Register • 2–5
register • 1–14
register file • 3–20
Vectorization factor • 1–21, 1–22
Vectorizing compiler • 1–8, 1–14
VIB • 2–2
Virtual address • 2–7, 2–8, 2–11, 3–14
VSTL instruction • 3–21
VSYNC instruction • 3–9
VVADDL instruction • 3–21
W
Wall-clock time • 3–4
Writeback cache • 3–13
X
XMI
bus • 2–8, 2–13
interface • 2–16
Index–3