Technical data

Vector Processing Concepts

1.1.3 Vector Processor Advantages

Vector processors have the following advantages:

• A vector processor can use the full bandwidth of the memory system

for loading and storing an array. Unlike the scalar processor, which

accepts single values at a time from memory, the vector processor

accepts any number up to its limit, say 64 elements, at a time. The

vector processor processes all the elements together and returns them

to memory.

• The vector processor eliminates the need to check the array index as

often. Since all values, up to the vector processor limit, are operated

upon at the same time, the vector processor does not have to check

the index for each element and each operation.

• The vector processor can free the scalar processor to do further scalar

operations. While the vector processor is doing operations other than

transferring data to or from memory, the scalar processor can do other

functions. This process is in contrast to a scalar processor performing

a math operation where the scalar processor must wait until the

calculation is complete before proceeding.

• The vector processor runs certain types of applications very fast, since

it can be optimized for particular types of calculations.

1.2 TYPES OF VECTOR PROCESSORS

Vector processors are classiﬁed according to two basic criteria:

• How closely coupled they are to their scalar coprocessor—whether

they are attached or integrated

• How they retrieve vector data—whether they are memory or register

processors

1.2.1 Attached vs. Integrated Vector Processors

In general, there are two types of vector processors: attached and

integrated. An attached vector processor (also known as an array

processor) consists of auxiliary hardware attached to a host system

that consists of some number of scalar processors. An attached vector

processor, which generally has its own memory and instruction set,

can also access data residing in the host main memory. It is typically

attached by a standard I/O bus and is treated by a host processor as an

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