Technical data

VAX 6000 Series Vector Processor
operation to take place. The data from the register file chip flows to
the vector FPU chip.
Input data to the vector FPU chip comes over a 32-bit bus that is driven
twice per cycle, and results are returned on a separate 32-bit bus that is
driven once per cycle. The two operands for single-precision instructions
can be passed in one cycle, while double-precision operands require
two cycles. The FPU chip has a throughput of one cycle per single-
precision operation, two cycles per double-precision operations, and 10 or
22 cycles per single- or double-precision divide. Its pipeline delay varies
for different operations; for example, the pipeline delay is 5 cycles for
all longword-type instructions and is 6 cycles for all double-precision
instructions except multiply.
2.4.1 Vector Register File Chip
The vector register file chip is the interface between the floating-point
processor and the rest of the vector module. Among its features are:
• It contains one quarter of the storage needed to implement the vector
registers defined by the VAX vector architecture (2 Kbytes/Verse).
• It provides four ports on the register file: a 64-bit, read/write port to
the CD bus for loads and stores, a 32-bit (64-bit internal) read port for
operand A, a 32-bit (64-bit internal) read port for operand B, and a 32-
bit (64-bit internal) write port for results. A load or store instruction
can be writing or reading the registers at one port, and an arithmetic
instruction can be reading its operands out of two other ports, and
another arithmetic instruction can be writing its results from still
another port. All three operations can be done in parallel. When two
longword operands are packed into the quadword, two separate vector
register file chips can each select the appropriate longword.
• It contains registers for holding two instructions, two scalar operands,
the vector length embedded in each instruction, and the vector mask.
• It performs the vector logical and vector merge instructions and
formats integer operations so that they can be executed by the FPU.
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