Technical data

Contents
1.10.3 Crossover Point
1–22
CHAPTER 2 VAX 6000 SERIES VECTOR PROCESSOR 2–1
2.1 OVERVIEW 2–2
2.2 BLOCK DIAGRAM 2–3
2.3 VECTOR CONTROL UNIT 2–5
2.4 ARITHMETIC UNIT 2–5
2.4.1 Vector Register File Chip 2–6
2.4.2 Vector Floating-Point Unit Chip 2–7
2.5 LOAD/STORE UNIT 2–7
2.6 VECTOR PROCESSOR REGISTERS 2–9
2.7 MEMORY MANAGEMENT 2–11
2.7.1 Translation-Not-Valid Fault 2–11
2.7.2 Modify Flows 2–11
2.7.3 Memory Management Fault Priorities 2–12
2.7.4 Address Space Translation 2–12
2.7.5 Translation Buffer 2–12
2.8 CACHE MEMORY 2–13
2.8.1 Cache Organization 2–13
2.8.2 Cache Coherency 2–16
2.9 VECTOR PIPELINING 2–17
2.9.1 Vector Issue Unit 2–17
2.9.2 Load/Store Unit 2–18
2.9.3 Arithmetic Unit 2–19
2.10 INSTRUCTION EXECUTION 2–21
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