Technical data

VAX 6000 Series Vector Processor
corresponding register file address is presented to the four register file
chips. The data and addresses are automatically aligned for load and
store operations to permit the correct reading and writing of the register
file and cache data RAMs. Up to four cache misses can be outstanding
before the read data for the first miss returns, and hits can be taken
under misses. Cache parity errors cause the cache to be disabled, the
instruction retried, and when the instruction completes, a soft error
interrupt is sent to the scalar processor.
A duplicate copy of the cache tag store is maintained for filtering cache
invalidates from the main memory bus. The cache is write through,
with a 32-element write buffer, and memory read instructions that hit in
the cache can start while the memory write instructions are emptying the
write buffer. The cache fill size is 32 bytes. The entire process is pipelined
so that a new 64-bit word can be read or written each cycle.
The load/store unit implements the following functions:
• Execution of all load, store, gather, and scatter instructions.
• Virtual address generation logic for memory references.
• Virtual to physical address translation logic, using a translation
buffer. A 136-entry TB is part of the load/store unit. The load/store
unit also contains the data path and control necessary to implement
full VAX memory management (with assistance from the scalar CPU).
• Cache control. The load/store unit supports the tag and data store for
a 1-Mbyte write-through data cache. It also supports a duplicate tag
store for invalidate filtering.
• XMI interface. The load/store unit serves as the interface between
the vector module and the XMI bus. This includes support for four
outstanding cache misses on read requests and a 32-entry write buffer
to permit half the data from one store/scatter instruction to be held
in the buffer. The performance of the high-speed CD bus can thus be
isolated from the performance impact of the slower XMI bus.
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