Technical data

VAX 6000 Series Vector Processor
2.7 MEMORY MANAGEMENT
The vector processor implements memory management as described in
the VAX Architecture Reference Manual.
The 32-bit virtual address is partitioned as shown in Figure 2–4.
Figure 2–4 Virtual Address Format
31 30 29 9 8 0
msb-0531-90
Virtual Page Number Byte in Page
Access mode
0,0 = P0 Space
0,1 = P1 Space
1,0 = S Space
1,1 = Reserved (virtual address causes length violation)
2.7.1 Translation-Not-Valid Fault
If the V bit = 0 for a page table entry (PTE) which is being used for
address translation, and no access violation (ACV) fault has occurred,
then the vector module passes status back to the scalar CPU indicating a
translation-not-valid (TNV) fault has occurred.
2.7.2 Modify Flows
If the PTE for the page being accessed has V bit = 1, access is a write,
no ACV fault has occurred, and the Modify (M) bit is not set, then the
memory management unit enters the modify flows. The load/store unit
sets the PTE M bit and continues.
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