Technical data

VAX 6000 Series Vector Processor

2.7.3 Memory Management Fault Priorities

Table 2–1 shows the priority order, from highest to lowest, by which the

vector processor reports faults.

Table 2–1 Memory Management Fault Prioritization

ACV Alignment TNV I/O Modify Error Reported

1 x x x x ACV vector, ACV

parameter

1 1 x x x ACV vector, align

parameter

0 0 1 x x TNV vector, TNV

parameter

1 0 0 1 x ACV vector, IOREF

parameter

0 0 0 0 1 Execute modify ﬂows

0 0 0 0 0 None; reference OK

2.7.4 Address Space Translation

The memory management hardware translates virtual to physical

addresses using the VAX Architecture Reference Manual requirements

for vector processors.

2.7.5 Translation Buffer

The translation buffer (TB) contains 136 page table entries (PTEs). The

TB has 68 associative tags with two PTEs per tag. The TB uses a round-

robin replacement algorithm. When a TB miss occurs, two PTEs (one

quadword) are fetched from cache. If the fetch from cache results in a

cache miss, eight PTEs (one hexword) are loaded into cache from main

memory. Two PTEs are installed in the TB.

The TB can be invalidated by executing a translation buffer ﬂush. This

is accomplished either by writing the VTBIA register or by writing the

VTBIS register with the desired virtual address to invalidate a single

location.

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