Technical data

VAX 6000 Series Vector Processor
2.8 CACHE MEMORY
The vector module implements a single-level, direct-mapped cache. In
addition, the load/store unit can hold the data and addresses for one
complete vector store or scatter instruction. Figure 2–5 shows the flow of
address and data in the load/store pipeline.
Each stage is a single or multiple stage based on the 44.44-ns vector
module clock. The XMI stage is a multiple of 64 ns, and the time taken
depends on the transaction type and the XMI bus activity. All memory
references must flow through the cache stage.
Figure 2–5 Address/Data Flow in Load/Store Pipeline
msb-0532-90
Virtual
Address
Generation
Virtual
To Phys.
Translate
Cache
Lookup/
Compare
Data
Transfer
Stage
XMI
Read Miss
2.8.1 Cache Organization
The vector processor implements a 1-Mbyte cache, direct-mapped, with a
fill of a hexword (block) and a hexword allocate (block size). The cache is
read allocate, no-write allocate, and write through. There are 32K tags,
and each tag maps one hexword block. Each tag contains one block valid
bit, a 9-bit tag, and one parity bit. Each data block contains 32 bytes and
8 parity bits, one for each longword.
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