Technical data

VAX 6000 Series Vector Processor
Associated with each of the 32K main tags is a duplicate tag in the
XMI interface. This tag is allocated in parallel with the main tag and is
used for determining invalidates. All XMI write command/address cycles
are compared with the duplicate tag data to determine if an invalidate
should take place. The resulting invalidate is placed in a queue for
subsequent processing in the main tag store. Figure 2–6 shows the cache
arrangement. Figure 2–7 shows how the physical address is divided.
Figure 2–6 Cache Arrangement
msb-0573-90
Tag
<Array>
QW0QW1QW2QW3 TAG
Data Array
Figure 2–7 Physical Address Division
msb-0572-90
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Tag Row Select
QWA
LWA
0
I/O
The physical address passed to the cache is 27 bits long and is longword
aligned. Bit <29> is never passed to the cache, because an I/O space
reference generates a memory management exception in the translation
buffer.Bits <28:20> are compared to the tag field. Bits <19:5> provide the
row select for the cache, bits <4:3> supply the quadword address, and bit
<2> supplies the longword address.
2–14