Technical data

VAX 6000 Series Vector Processor
Figure 2–8 shows how the main tag memory is arranged. The main tag
is written with PA<28:20>, and the valid bit covers a hexword block. The
parity bit covers the tag and valid bits. The duplicate tag memory is
identical to the main tag memory.
Figure 2–9 shows the organization of the cache data. Each cache block
contains four quadwords, with eight longword parity bits.
Figure 2–8 Main Tag Memory Organization
10 9 8 7 6 5 4 3 2 1 0
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Tag DataV
PAR
Figure 2–9 Data Cache Logical Organization
LW 0
P
0
LW 1
P
1
LW 2
P
2
LW 3
P
3
LW 4
P
4
LW 5
P
5
LW 6
P
6
LW 7
P
7
QW0QW1
QW2
QW3
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