Technical data

VAX 6000 Series Vector Processor
2.8.2 Cache Coherency
All data cached by a processor must remain coherent with data in main
memory. This means that any write done by a processor or I/O device
must displace data cached by all processors.
The XMI interface in the load/store unit continuously monitors all XMI
write transactions. When a write is detected, the address is compared
with the contents of a duplicate tag store to determine if the write should
displace data in the main cache. If the write requires that the main cache
tag be invalidated, then an invalidate queue entry is generated. The
duplicate tag store is a copy of the main tag store. When a main cache
tag allocate is performed, the corresponding duplicate tag is also allocated.
When an invalidate request is generated, the duplicate tag is immediately
invalidated. This mechanism permits full bandwidth operation of the
main cache without missing an invalidate request.
The invalidate queue is 16 entries long. In its quiescent state the load
/store unit can process invalidates faster than the XMI can generate them.
However, during execution of a load or store instruction, the invalidate
queue can fill to a level where normal processing must cease, and the
invalidate queue is then emptied before an overflow occurs. The number
of entries before this mechanism is enabled is nine.
2–16