Technical data

VAX 6000 Series Vector Processor

The availability of registers is handled by a method called scoreboarding.

The rules governing register availability depend on the type of instruction

to be issued.

• For a load instruction, the register to be loaded must not be modiﬁed

by any currently executing (arithmetic) instruction, and it must not

be modiﬁed or used as input by any currently deferred (arithmetic)

instruction.

• For a store instruction, the register to be stored must not be modiﬁed

by any currently executing or deferred instruction, but it may be in

use as input. The exception is when a chain into store may occur.

In this case the store instruction can be issued while the chaining

arithmetic instruction is still executing.

• For a scatter or gather instruction, the restrictions for a load or store

instruction apply, but also the register containing the offset to be

used in the scatter or gather instruction must not be modiﬁed by any

currently executing or deferred instruction.

• For a load or store under mask instruction, the restrictions for a load

or store instruction apply, but also the mask register must not be

modiﬁed by any currently executing or deferred instruction.

• An arithmetic instruction may be issued as soon as the deferred

instruction queue of the arithmetic unit is free. Register checking for

these instructions is handled by the arithmetic unit.

In general, there must be no outstanding writes to a needed register from

prior instructions, and the destination register of the instruction must not

be used by a currently deferred instruction.

Once an instruction is issued, it may take multiple cycles before the result

of the calculation is available. Meanwhile, in the next cycle the next

instruction can be decoded and, if all its issue conditions are satisﬁed, it

can be issued.

2.9.2 Load/Store Unit

The load/store unit handles all cache and memory access for the vector

module. The load/store unit includes a ﬁve-segment pipeline that can

accept a new instruction every cycle. In general, the load/store pipeline

handles a single element request at a time. The exception occurs when a

load instruction is acting on single-precision, unity vector stride data. In

this special case, consecutive elements are paired and then each pair is

handled as a single request by the load/store pipeline.

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