Technical data

VAX 6000 Series Vector Processor
Figure 2–11 Vector Arithmetic Unit
msb-0585-90
Integer
Instruction
Conversion
Result
Conversion
Logical
or Merge
Instruction
FPU
FPU
...
...
1 cycle 1 cycle
An instruction continues executing until all results are completed. A
deferred arithmetic instruction begins execution after the instruction in
the pipeline completes or when all the following conditions are met:
• The deferred instruction must not be a "short" instruction; that is,
the vectors used by the instruction must be at least eight elements in
length.
• The current instruction must not be a "long" instruction; that is, the
instruction must not require more than two cycles per element to
execute. (The divide instructions are the only "long" instructions.)
In other words, overlap of instruction execution can occur if the results of
the deferred instruction will not be completed before the last results from
the current instruction. The overlap of instructions will be particularly
significant for shorter vectors.
All instructions, except floating-point divide instructions, are fully
pipelined. For increased performance all arithmetic instructions are
executed by four parallel pipelines.
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