Technical data

3
Optimizing with MACRO-32
This chapter discusses optimization features of the VAX 6000 series vector
processor. Appendix A provides additional optimization examples. This
chapter includes the following sections:
• Vectorization
• Crossover Point
• Scalar/Vector Synchronization
• Instruction Flow
• Overlap of Arithmetic and Load/Store Instructions
• Out-of-Order Instruction Execution
• Chaining
• Cache
• Stride/Translation Buffer Miss
• Register Reuse
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