Technical data

Optimizing with MACRO-32
serviced, the SYNC may be returned to through a Return from Exception
or Interrupt (REI) instruction.
SYNC only affects the scalar/vector processor pair that executed it. It has
no effect on other processors in a multiprocessor system.
3.3.2 Scalar/Vector Memory Synchronization
The scalar processor and the vector processor can access memory at the
same time during:
• Asynchronous memory management mode
• Synchronous memory management mode, after the vector processor
indicates no memory management exceptions occurred
When the scalar processor and the vector processor access memory at
the same time, it may be desirable to synchronize their accesses. Using
an MFVP from MSYNC vector control register causes the scalar CPU to
stall until previous memory accesses by either the vector processor or the
scalar processor are completed and visible to the other. MSYNC is for
user software.
Scalar/vector memory synchronization allows software to ensure that the
memory activity of the scalar/vector processor pair has ceased and that
the resultant memory writes have been made visible to each processor
in the pair before the pair’s scalar processor proceeds with the next
instruction. Two ways are provided to ensure scalar/vector memory
synchronization:
• Using MSYNC, which is implemented by the MFVP instruction
• Using the Move From Processor Register (MFPR) instruction to read
the Vector Memory Activity Check (VMAC) internal processor register
In the following example, both the vector processor load instruction
(VLDL) and the scalar processor move instruction (MOVF) would be
using the same BASE memory. MSYNC ensures that the load instruction
completes before beginning the move instruction.
VLDL BASE, #4, V1
MSYNC R0
MOVF#^F3.0, BASE
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