Technical data

Optimizing with MACRO-32
Scalar/vector memory synchronization does not mean that previously
issued vector memory instructions have completed; it only means
that the vector and scalar processor are no longer performing memory
operations. While both VMAC and MSYNC provide scalar/vector memory
synchronization, MSYNC performs significantly more than just that
function. In addition, VMAC and MSYNC differ in their exception
behavior.
Note that scalar/vector memory synchronization only affects the processor
pair that executed it. Other processors in a multiprocessor system are not
affected. Scalar/vector memory synchronization does not ensure that the
writes made by one scalar/vector pair are visible to any other scalar or
vector processor.
Software can make data visible and shared between a scalar/vector pair
and other scalar and vector processors by using the mechanisms described
in the VAX Architecture Reference Manual. Software must first make
a memory write by the vector processor visible to its associated scalar
processor through scalar/vector memory synchronization synchronization)
before making the write visible to other processors. Without performing
this scalar/vector synchronization, it is unpredictable whether the vector
memory write will be made visible to other processors even by the
mechanisms described in the VAX Architecture Reference Manual.
Note that waiting for VPSR<BSY> to be clear does not guarantee that a
vector write is visible to the scalar processor.
3.3.2.1 Memory Instruction Synchronization (MSYNC)
Once it issues MSYNC, the scalar processor executes no further
instructions until MSYNC completes or faults.
When MSYNC completes, a longword value (which is unpredictable) is
returned to the scalar processor, which writes it to the scalar destination
of the MFVP instruction. The scalar processor then proceeds to execute
the next instruction.
Arithmetic and asynchronous memory management exceptions
encountered by previous vector instructions can cause MSYNC to fault.
When MSYNC faults, all previously issued scalar and vector memory
instructions may not have finished. In this case, the scalar processor
writes no longword value to the scalar destination of the MFVP.
Depending on the exception encountered by the vector processor, the
MSYNC takes a vector processor disabled fault or memory management
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