Technical data

Optimizing with MACRO-32
fault. After the fault has been serviced, the MSYNC may be returned to
through a Return from Exception or Interrupt (REI) instruction.
3.3.2.2 Memory Activity Completion Synchronization (VMAC)
Privileged software needs a way to ensure scalar/vector memory
synchronization that will not result in any exceptions being reported.
Reading the Vector Memory Activity Check (VMAC) internal processor
register with the privileged Move From Processor Register (MFPR)
instruction is provided for these situations. It is especially useful for
context switching.
Once an MFPR from VMAC is issued by the scalar processor, the scalar
processor executes no further instructions until all vector and scalar
memory activities have ceased; all resultant memory writes have been
made visible to both the scalar and vector processor; and a longword
value (which is unpredictable) is returned to the scalar processor. After
writing the longword value to the scalar destination of the MFPR, the
scalar processor then proceeds to execute the next instruction.
Vector arithmetic and memory management exceptions of previous vector
instructions never fault a privileged MFPR from the Vector Memory
Activity Check Register and never suspend its execution.
3.3.3 Memory Synchronization Within the Vector Processor (VSYNC)
The vector processor can concurrently execute a number of vector memory
instructions through the use of multiple load/store paths to memory.
When it is necessary to synchronize the accesses of multiple vector
memory instructions, the MSYNC instruction can be used; however, there
are cases for which this instruction does more than is needed. If it is
known that only synchronization between the memory accesses of vector
instructions is required, the Synchronize Vector Memory Access (VSYNC)
instruction is more efficient.
If a conflict results within the vector processor for accessing memory,
a VSYNC instruction can be used. VSYNC ensures that the current
memory access instruction is complete before executing another. This
instruction does not affect scalar processor memory access instructions.
VSYNC orders the conflicting memory accesses of vector memory
instructions issued after VSYNC with those of vector memory instructions
issued before VSYNC. Specifically, VSYNC forces the access of a memory
location by any subsequent vector memory instruction to wait for (depend
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