Technical data

Optimizing with MACRO-32

upon) the completion of all prior conﬂicting accesses of that location by

previous vector memory instructions.

VSYNC does not have any synchronizing effect between scalar and vector

memory access instructions. VSYNC also has no synchronizing effect

between vector load instructions because multiple load accesses cannot

conﬂict. It also does not ensure that previous vector memory management

exceptions are reported to the scalar processor.

3.3.4 Exceptions

There are two categories of exceptions within the vector processor:

• Imprecise exceptions

• Precise exceptions

3.3.4.1 Imprecise Exceptions

Imprecise exceptions can occur within the vector processor when

arithmetic instructions are processing. They may be caused by typical

arithmetic problems such as division by zero or underﬂow. Because the

vector processor can execute instructions out of order, it is not possible

to determine the instruction that caused the exception from the updated

program counter (PC). The PC in the scalar processor is pointing further

down the instruction stream and cannot be backed up to point at the

failing instruction. To report the exception condition in this case, the

vector processor disables itself so that the scalar processor will take a

vector disable fault when it attempts to dispatch a vector instruction. The

vector disable fault handler then determines the cause. When this type

of exception occurs, the vector controller sets a bit in the register mask

in the Vector Arithmetic Exception Register (VAER) IPR to indicate the

destination vector register which received data from the exception. It

then informs the scalar CPU of the exception.

When debugging code, it is often necessary to be able to ﬁnd the precise

instruction causing the problem. Inserting a SYNC instruction after

each arithmetic instruction will cause the machine to run in precise

mode, waiting for each instruction to complete before executing the next.

However, it will run much slower than when imprecise exceptions are

allowed to occur.

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