Technical data

Optimizing with MACRO-32
Example 3–4 Deferred Arithmetic Instruction Queue
Instruction Sequence
VVADDL V1,V2,V3
VVMULL V3,V1,V4
VLDL base,#4,V2
Execution without Deferred Instruction Queue
Issue VVADDL IEEEEEEEE
Issue VVMULL IEEEEEEEE
Issue VLDL IEEEEEEEEEEEEEE
Execution with Deferred Instruction Queue
Issue VVADDL IEEEEEEEE
Issue deferred VVMULL I.......EEEEEEEE
Issue VLDL IEEEEEEEEEEEEEE
In Example 3–5 the VLDL instruction cannot begin before VVMULL
because VVMULL needs data in V3 before the VLDL takes place.
Example 3–5 A Load Stalled due to an Arithmetic Instruction
VVADDL V1,V2,V3 IEEEEEEEE
VVMULL V3,V4,V5 I.......EEEEEEEE
VLDL base,#4,V3 IEEEEEEEEEEEEEE
To take advantage of the deferred instruction queue, close attention to
instruction ordering and register use is required. Generally, a divide
or two other arithmetic instructions should precede each load or store
instruction. (In the case of divide instructions, multiple load/store
instructions can be overlapped with a single divide instruction.) This
is not always possible, since initial loads are usually necessary and
there may not be two arithmetic instructions per load/store. Also, some
instruction ordering is dictated by the use of the data. But even with
these restrictions, it is still important to watch for potential instruction
execution overlap.
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