Specifications

12
TURBOchannel Bus Support
This chapter discusses TURBOchannel support in the OpenVMS AXP operating
system and describes TURBOchannel concepts and implementations on AXP
platforms.
12.1 TURBOchannel Overview
The TURBOchannel is a synchronous I/O bus with a 32 bit multiplexed address
and data path. It can operate at clock frequencies from 12.5 to 25 MHz with
a peak DMA bandwidth of 100 Mbytes per second. The TURBOchannel
architecture distinguishes between a system module, containing the processor
/memory system, and option modules, which are generally I/O controllers. The
TURBOchannel is asymmetric, in that the system module can read or write
option modules and option modules can read or write the system module, but
direct communication between option modules is not allowed.
Option modules occupy TURBOchannel backplane slots. The backplane slot
determines the base address of the option module. Each slot has from 4 to
512 Mbytes of address space. The actual address space allocated to each
TURBOchannel slot and the base address of each slot is system specific. The
TURBOchannel supports the notion of integral options, which are logical
TURBOchannel options, physically implemented on the system module,
that do not occupy backplane slots. I/O transactions on the TURBOchannel
are defined as loads and stores from the system module to option module
addresses. I/O transaction addresses on the TURBOchannel are 29 bits,
with the two least significant bits implicitly zero. DMA transactions on the
TURBOchannel are defined as option module reads and writes to system memory.
The TURBOchannel architecture defines a 34 bit byte address, with the two least
significant bits implicitly zero, for DMA address space. The actual DMA address
space is system specific. All TURBOchannel DMA transfers are in units of 32
bit longwords, and can be of any length up to a system specific limit. Interrupts
on the TURBOchannel are associated with the TURBOchannel slots and are
level sensitive. The interrupt priority of each slot is system specific. An option
must maintain its interrupt signal until software explicitly clears the interrupt
condition at the option. All TURBOchannel options must implement an Option
ROM, which contains information about the option module.
12.2 TURBOchannel on DEC 3000 Model 500
The following sections cover the DEC 3000 Model 500 TURBOchannel address
map, DEC 3000 Model 500 TURBOchannel dense and sparse space addressing,
register access, DMA and map register support, bus interface hardware registers,
I/O space mapping, and loading a driver for a TURBOchannel option.
12–1