Specifications

TURBOchannel Bus Support
12.2 TURBOchannel on DEC 3000 Model 500
12.2.1 DEC 3000 Model 500 TURBOchannel Address Map
The TURBOchannel bus on a DEC 3000 Model 500 system contains 6 option
slots, labelled 0-5 by OpenVMS AXP. The TURBOchannel address map for DEC
3000 Model 500 is shown below:
DEC 3000 Model 500 TURBOchannel Address Map
Slot Base Physical Addresse Space
0 1 0000 0000 128 MB Slot 0 Dense space
1 0800 0000 128 MB Reserved
1 1000 0000 256 MB Slot 0 Sparse space
1 1 2000 0000 128 MB Slot 1 Dense space
1 2800 0000 128 MB Reserved
1 3000 0000 256 MB Slot 1 Sparse space
2 1 4000 0000 128 MB Slot 2 Dense space
1 4800 0000 128 MB Reserved
1 5000 0000 256 MB Slot 2 Sparse space
3 1 6000 0000 128 MB Slot 3 Dense space
1 6800 0000 128 MB Reserved
1 7000 0000 256 MB Slot 3 Sparse space
4 1 8000 0000 128 MB Slot 4 Dense space
1 8800 0000 128 MB Reserved
1 9000 0000 256 MB Slot 4 Sparse space
5 1 A000 0000 128 MB Slot 5 Dense space
1 A800 0000 128 MB Reserved
1 B000 0000 256 MB Slot 5 Sparse space
DEC 3000 Model 500 also contains 3 integral options–the integrated SCSI
adapter (TURBOchannel slot 6), the Core I/O subsystem (TURBOchannel slot 7),
and an integrated graphics controller (TURBOchannel slot 8). Symbols defining
the slot base physical addresses for the TURBOchannel on DEC 3000 Model 500
can be found in file [LIB.LIS]IO0402DEF.SDL. These symbols are of the form
IO0402$Q_SLOTx_DENSE_BASE or IO0402$Q_SLOTx_SPARSE_BASE.
12.2.2 Dense and Sparse Space Addressing
The DEC 3000 Model 500 TURBOchannel bus interface hardware maps every
byte of TURBOchannel address space into two distinct address spaces. These
address spaces are called dense and sparse address space. Dense space addresses
correspond to "normal" addresses, where successive longword addresses are 4
bytes apart. In sparse space, the address space has been expanded by a factor of
two, so that successive longword addresses are actually 8 bytes apart. This allows
space for a byte mask to be supplied on I/O write transactions. This can be better
illustrated by an example.
Suppose an option implements two longword registers as shown in Figure 12–1.
12–2