Specifications

PCI Bus Support

This chapter discusses PCI (Peripheral Component Interconnect) bus concepts

and implementations on AXP platforms.

Other PCI bus characteristics include the following:

• 32 bit address.

• 32 bit data.

• Separate memory, I/O, and conﬁguration space.

Each space (memory, I/O, and conﬁguration) is a separate 32 bit address

space. 64 bit addressing is also deﬁned for PCI memory space.

• Bus operation is synchronous at frequencies up to 33 MHZ.

33 MHz operation yields 132 MB/second peak performance: 33 * 10^6

cycles/second * 4 bytes/cycle = 132 MB/second. Interrupts are not part of the

bus speciﬁcation.

The PCI bus has been designed with the notion of a bus hierarchy. The PCI

bus closest to the CPU is accessed through a Host/PCI bridge, and is called the

host PCI. Remote PCI buses are accessed through PCI-PCI bridge chips that are

connected to PCI buses closer to the processor.

Note

OpenVMS AXP V6.1 supports single function PCI devices. There is no

support for PCI-PCI bridges or multifunction PCI devices. Support for

PCI-PCI bridges and multifunction PCI devices will appear in a future

release.

13.1 PCI Addressing

PCI deﬁnes three separate address spaces: memory, I/O, and conﬁguration.

PCI Conﬁguration space is intended for use primarily during booting and

conﬁguration, although it is required to be accessible at all times. PCI I/O

space is similar to EISA I/O space, and is generally used for registers and

control functions that require byte and word length access. PCI memory space

is intended for devices with memory buffers that require memory address space,

such as frame buffers. PCI memory space is also intended for device registers.

On the hardware level, one accesses the different address spaces (memory, I/O,

or conﬁguration) by using different PCI transaction types. That is, for a read to

memory space, the hardware generates a Mem_Read cycle, while for a read to I/O

space, the hardware generates an IO_Read cycle, and for a read to Conﬁguration

Space, the hardware generates a Conﬁg_Read cycle. Digital platforms use a

13–1