Specifications

PCI Bus Support
13.2 PCI Configuration Space
A device may implement up to 6 Base Address registers. This allows a device
to use up to 6 separate address ranges for device registers or memory buffers.
Generally a device will only require one or two Base Address registers.
The predefined Configuration Space header and the Base Address registers enable
system independent software to locate all PCI devices in the system address
space, and to assign address space to devices in a conflict-free configuration. As
mentioned previously, the PCI address space assignment is done by the console
on Digital AXP platforms.
13.3 PCI as an I/O Bus on AXP Platforms
The Alpha I/O Task Force has defined a standard reference model for I/O bus and
device access. The intent of this model is to move away from hardware mailboxes
and toward a direct, swizzle space mechanism for device register access. PCI
requirements are a driving force behind this model.
The reference model says that platforms will provide access to PCI memory and
I/O space through different address regions in the platform physical address
space.
Access to PCI I/O space is through a swizzle space address encoding with a 5 bit
address shift. Only a small portion of the 4 GB PCI I/O space is addressible by
the CPU (due to the 5 bit address swizzle). Some platforms allow access to 128
MB of PCI I/O space, while others may allow access to only the lowest 64 KB
of PCI I/O space. Lack of addressibility of the entire PCI I/O address space is
not seen as a problem because PCI devices are encouraged to implement device
registers in PCI memory space, and INTEL processors can only access 64 KB of
PCI I/O space.
PCI memory space is accessible in both dense and swizzle space. There are
separate platform physical address regions for swizzle space and dense space.
The access characteristics of each space are different. Swizzle space (5 bit address
shift) is intended for byte, word, long, and quad access granularity. The size of
the transfer and which bytes will be transfered are encoded in bits 6:3 of the CPU
address. Software must align the data in the correct byte lanes. To maintain
ordering of data transfers, software must issue memory barriers after each device
access. Device control registers that are implemented in PCI memory space
should be assigned (by the console) to swizzle space.
The minimum access granularity of dense space is longword. In dense space,
the Alpha CPU address maps directly to the PCI address–there is no address
bit shifting as in swizzle space. Platforms are permitted to implement read
prefetching and write merging in dense space. Device control registers should not
be placed in dense space. Dense space is intended for frame buffers and other
on-chip buffers with memory-like behaviour.
13.4 PCI Device Interrupts
The PCI specification does not define an interrupt mechanism for I/O device
interrupts. Some systems implement Intel-style interrupts using PC style
interrupt controller chips, such as the 8259. Other systems implement custom
interrupt handling logic.
In general, a distinction is made between "motherboard" PCI devices, which are
built into the system and always present, and option slot devices. A motherboard
device generally interrupts through a unique input on the system interrupt
controller.
13–3