Specifications

14
EISA and ISA Bus Support
This chapter describes the evolution of the Extended Industry Standard
Architecture (EISA) bus, provides backround information on the Industry
Standard Architecture (ISA) bus, and discusses the EISA bus on the DEC 2000
system.
14.1 Evolution of the EISA Bus
The EISA bus is an extension of the ISA bus. ISA started as the 8 bit bus in
early IBM personal computers and was based on the INTEL 8088 chip. The I/O
cards used an 8 bit data bus, and a 16 bit address bus. To save decode logic on
the cards, they only decoded the lower 10 address bits for I/O space. Most cards
had their resources (IRQ, DMA, IO Ports, Memory Range) hardwired into them.
There were 8 interrupt levels (provided by an INTEL 8259 chip), and 4 DMA
Channels (provided by an INTEL 8237 chip) available. The configuration of the
machine was limited by these resources. As the CPU chips got faster, and system
size increased, the ISA bus functionality was increased to offer 15 interrupt lines,
7 DMA channels, and a 16 bit data bus to/from I/O. This is known as 16 bit
ISA. The cards still decoded only 10 bits in I/O space. To differentiate between
memory and I/O space addresses the cards used the AEN signal distributed by
the CPU. If AEN was asserted, the cards were enabled to look at the address
on the bus. If it matched their IO Port address range, they responded. While
DMA was happening AEN was deasserted so that no card would accidentally
decode a DMA address as an IO space access. At this point, IBM archictected a
new I/O bus, Microchannel Architecture (MCA), which was totally incompatable
with the ISA bus. This led the industry to design the EISA bus. Designed to
accept both 8 and 16 bit ISA cards as well as EISA cards, the EISA bus allowed
customers to protect their current investment in PC hardware. EISA extended
the data path to addr[9:8]32 bits, added software readable product ID’s (essential
to automatic configuration), slot specific I/O addressing, and active-low level
sensitive interrupts (allowing true sharing of IRQ levels).
To allow ISA cards to work in the new EISA systems, slot specific AEN signals
were added. In I/O space addr[9:8]32 were not equal to 00, it was assumed that
the access was intended for an old style ISA card, and AENx was asserted at all
slots to allow the proper card to decode it. If I/O address bits addr[9:8]32 = 00,
then the reference is assumed to be to a new EISA card, and addr[9:8]32 are used
to select which slot answers the access (via AENx).
Note that the ISA bus is the prevalent bus seen in PCs today. There are still both
8 and 16 bit ISA cards in many machines. EISA offers higher bandwidth, due to
the increased data path size, thus is more suited to the faster microprocessors
available today. Also note that the EISA bus functionality is a superset of the
ISA bus. Anything that works on the ISA bus will also work on the EISA bus,
however, the reverse is not true. EISA cards will not work on an ISA bus.
14–1