Specifications

EISA and ISA Bus Support
14.7 EISA Bus Support on DEC 2000
14.7 EISA Bus Support on DEC 2000
The following sections describe the EISA Bus Support offered on DEC 2000.
Specifically, they describe the following:
• The DEC 2000 System Address map
• The addressing scheme used for byte access to EISA registers
• Interrupt processing
• DMA channels
• OpenVMS AXP provided bus support routines
14.7.1 DEC 2000 System Address Map
The addressing scheme on DEC 2000 is shown in the following table.
cpu cpu cpu cpu Effect
Addr33:32 Addr 31 Addr 30 Addr29:28
00 MBZ MBZ MBZ Local Memory
cAddr 31:28 MBZ
01 1 MBZ MBZ EISA INTA cycle
(I/O space)
cA 31:5 MBZ
cA 4:0 SBZ
01 1 0 0x FEPROM #0 cA 28:9w
= addr for up to
1MB of ROM,
cA 8:0 SBZ
Data in low byte
01 1 0 1x FEPROM #1 cA 28:9
= addr for up to
1MB of ROM
cA 8:0 SBZ
01 1 1 00 Combo Chip byte
ComboAddr ..9 from
cA ..9 cA 8:0 SBZ
Data in low byte
01 1 1 01 Host Address
Extension Reg
cA 27:0 SBZ
01 1 1 10 System Control Reg
cA 27:0 SBZ
01 1 1 11 Spare Register
10 x x xx EISA Memory
A 31:25 - HAE 6:0
A 24:2 -cA 31:9
Length/Offset from
11 x x xx EISA IO
A 31:25 - HAE 6:0
A 24:2 -cA 31:9
Length/Offset from
cA 8:5
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