Specifications

EISA and ISA Bus Support
14.7 EISA Bus Support on DEC 2000
14.7.1.1 DEC 2000 Address Space
Figure 14–1 shows the DEC 2000 address map as seen by the CPU.
Figure 14–1 DEC 2000 Address Map
DEC 2000 address map as seen by CPU
Host
memory
256 MB
cA<33:0>
3 FFFF FFFF
0 0000 0000
0 0FFF FFFF
01 0000 0000
01 8000 0000
01 A000 0000
01 C000 0000
01 D000 0000
01 E000 0000
01 F000 0000
2 0000 0000
2 FFFF FFFF
3 0000 0000
EISA
memory
space
sparse
EISA
I/O
space
sparse
INTA Cycle Special Address
FEPROM #0 starting Address
FEPROM #1 starting Address
Combo Chip starting Address
Host Address Extension Register Special Address
System Control Register Special Address
Spare Register
32 MB
32 MB
Equivalent EISA Memory Space
0000 0000
01FF FFFF
0000
Equivalent EISA I/O Space
Only 64 KB of EISA I/O
space is necessary
(4K per slot * max 16 slots)
ZK−6739A−GE
14.7.1.2 DEC 2000 System Memory (0-FFF.FFFF)
The DEC 2000 system will support up to 256MB of main memory, addressable
using cpu address bits <27:0>. Note that the memory will not respond to access
by any device other than the CPU in the upper half-megabyte of the first
megabyte of memory (0.5-1MB). This mean that no DMA is allowed into that
address range. This restriction is to allow E/ISA devices with on board memory
buffers to address those buffers in the first megabyte of EISA memory space.
14–7