Specifications

EISA and ISA Bus Support
14.7 EISA Bus Support on DEC 2000
14.7.1.3 INTA Cycle Access (1.0000.0000)
The interrupt scheme defined for this machine includes an access to the 82357
chip in order to find out which IRQ level is requesting an interrupt. The
mechanism by which this is accomplished on the DEC 2000 is via the special
address, 1.0000.0000 . Reading this address will cause hardware to issue an
INTA cycle over the EISA bus, which is responded to by the 82357 Interrupt
Controller. The first INTA cycle causes the controller to lock the request register
for priority resolution, and the second read to this address causes the controller
to return a vector in the low byte. This vector indicates the EISA irq currently
being serviced (irq + 8 is returned). Device drivers should never need to access
this register. The INTA cycle is performed by PALcode.
14.7.1.4 NVRAM Access (1.8000.0000, 1.A000.0000)
The Flash Rom on DEC 2000 stores console code and configuration information.
It is divided up into logical blocks of size 64K. The SRM console is contained in
the first 6 logical blocks, with the SRM EISA configuration information contained
in the 7th logical block. The Windows/NT console is contained in blocks 8 through
12, with the NT EISA configuration data contained in block 13. The remaining
blocks contain the Failsafe Loader. Device drivers should never access NVRAM
directly. Bus Support routines are provided as an interface to the configuration
data blocks (IOC$NODE_DATA, IOC$NODE_FUNCTION).
14.7.1.5 VTI VL82C106 Combination Chip (1.C000.0000)
The Combo chip is addressed starting at physical address 1.C000.0000. All
the port addresses given in the VTI Combo Chip spec are offset from that base
address. Refer to the Combo Chip spec for more details on register offsets. The
data returned from reads to this space is returned in the low byte, regardless of
the byte offset. This space is mapped into the processor’s virtual address space
by the Bus support code, and the VA can be found in the ADP$Q_CSR offset of
the COMBO ADP (TR # = 3), or in the IDB$Q_CSR field if your driver is loaded
via autoconfigure. It is important to note that the Combo Chip addresses need
to be swizzled before being put out on the bus. The combo chip offsets should be
shifted up by 9 bits before being put out over the bus by the driver. The hardware
then shifts them down when presenting them to the Combo chip. For example,
byte offset 3BC in combo chip space is used to address a parallel port register. In
order to get the proper physical address to map the following translation must
take place:
PA = 1.C000.0000 + 3BC ^ 9 = 1.C007.7800
Or, using the base VA from the Combo ADP, ADP$Q_CSR + 77800 would access
the register. The CRAM routines perform this address shifting for you when used
for register access.
14.7.1.6 Host Address Extension Register (1.D000.0000)
This register is used to extend the addressable space on DEC 2000. This 8 bit
register is used to form address bits <31:25> on the EISA bus. For the DEC 2000
implementation, this register is set to 0 by console, and is not used afterwards.
If this register will be changed or used in the future, synchronization issues will
have to be resolved. Device drivers should never access this register. OpenVMS
AXP assumes that this register is always zero.
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