Specifications

EISA and ISA Bus Support
14.7 EISA Bus Support on DEC 2000
EISA bus slot 4, and you want to read the product ID longword. The PID is
stored starting at offset C80. The address would be formed as follows:
PA = base_addr+( slot * 1000 + slot_offset) ^7 +
length_constant_for_longword
3.0000.0000 +( 4C80 ^ 7) + 060
3.0000.0000 + 264000 + 060 = 3.0026.4060
Mapping this PA would give access to the longword containing the PID for any
board in slot 4. Note also that the CRAM routines provided by the Bus Support
Code insulate the user from all this bit manipulation. The interface to these
handy routines is described in an earlier chapter. Note that the CRAM routines
expect the user to use the proper byte lane when reading or writing data from
the CRAM$Q_RDATA/CRAM$Q_WDATA fields of the CRAM. Specifically, if it is
intended to write a byte at byte offset 1 of a quadword, that data byte must be
placed in byte lane 1 of the CRAM$Q_WDATA quadword.
Note that for all ISA devices the slot number is considered to be 0. All ISA
devices respond to slot 0 addresses regardless of what is put into address bits
<15:12> on the EISA bus. If the slot offset has bits <9:8> = 00, then the ISA
devices don’t respond at all, if bits <9:8> != 00 then the ISA devices respond, no
matter what the "slot" bits (<15:12> ) are set to. Figure 14–4 shows an expanded
view of DEC 2000/EISA I/O space.
14–12