Specifications

EISA and ISA Bus Support
14.7 EISA Bus Support on DEC 2000
Figure 14–4 Expanded view of DEC 2000/EISA I/O Space
ZK−6742A−GE
DEC 2000 address map as seen by CPU
0000
EISA I/O space
3 0000 0000
3 0008 0000
3 0010 0000
System
board
1000
2000
3000
4000
5000
6000
Slot 6
Slot 1
4 KB
Slot 2
4 KB
Slot 3
Slot 4
Slot 5
3 0028 0000
3 0030 0000
3 0018 0000
3 0020 0000
System board
I/O ports
ISA board
ports
Slot 1
slot specific
I/O
512 KB
Slot 2
slot specific
I/O
512 KB
Slot 3
Slot 4
Slot 5
Slot 6
cA<33:0>
CPU/EISA address translation:
7 bit address shift
cA<31:9> cA<8:7> cA<6:5>
offset length
eisa<24:2> ByteEnable<3:0>
encode
14.7.2 Sparse Space
All I/O access on DEC 2000 is done in "sparse" space. There is no dense space.
Address bits <8:5> are used to select the length of the transaction and the
starting longword offsets as shown in the following table.
14–13