Specifications

EISA and ISA Bus Support
14.7 EISA Bus Support on DEC 2000
14.7.4 DMA on DEC 2000
There is no Scatter/Gather Map on DEC 2000. A DMA engine is provided for
those devices that don’t have Bus Master capability. 7 DMA channels exist in the
82357 chip. The channels are assigned as resources by the ECU. It is up to the
driver to set up the channel for operation via writes to the 82357 DMA registers.
IOC$NODE_DATA can be used to get the DMA channel assigned to a board. The
IOC$NODE_DATA interface is described below. A brief example is given, showing
one usage of a DMA channel. For complete details, please refer to the INTEL
82357 specification.
14.7.4.1 DMA Example
This example shows how the floppy driver on DEC 2000 made use of one of the
provided DMA channels. The floppy chip (82077) is resident on the Adaptech
SCSI board, but is considered to be a seperate device, using the ISA protocol. It
is hardcoded to use IRQ6, I/O ports 3F2h-3F7h, and DMA channel #2.
The driver allocates and maps a contiguous buffer to store the DMA data in
between the floppy device and the requestor. Then for each access it must set
up a number of DMA registers in the 82357 chip to program the channel for the
access. One sequence used to set up a channel looks as follows:
• Setup the channel in the desired mode, enable it as follows:
Command register, offset 8D0, enable the channel. Note channel 4 must
be enabled if device is using channels 0-3, as they are cascaded through
channel 4.
Mode Register, offsets B,D6, set the desired mode: chan 4 = cascade, and
set the assigned channel to be either read or write, depending on the
command to be issued.
• Set up the target address as follows:
Clear the byte pointer, offset C. This clears a byte pointer flip-flop which
indicates whether the high or low byte was accessed last. This must be
done prior to R/W of the address or word count registers.
Load the base addr register, offset 4. This byte register is written twice to
load the 16 bits of the base address register.
Load the low page register, offset 81. This byte register contains bits
<16:23> of the 32 bit target address
Load the high page register, offset 481. This is the high byte of the target
address.
• Load the transfer count registers as follows:
Clear the byte pointer once again
Load base count register, offset 5. Note it is necessary to load #_of_bytes_
to_transfer-1inthecount register due to the HW of the 82357 chip.
Load the count register, offset 405. Load the 2nd byte of the count
register.
• Enable the channel, fill the command silo of the 82077 chip, and let it rip!
Set Mask Write register, offset A. Set the bits enabling channel 2 to do
DMA.
Perform the DMA action.
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