Specifications

15
Futurebus+ Bus Support
This chapter discusses base Futurebus+ support in the OpenVMS AXP operating
system. First a general description of Futurebus+ concepts is given, followed by
a description of Futurebus+ support in the operating system and a description of
Futurebus+ support on the DEC 4000 and DEC 10000/7000 platforms.
15.1 Futurebus+ Overview
Futurebus+ is an industry standard bus defined by IEEE standards 896.1
(Logical Layer), 896.2 (Physical Layer and Profiles), 896.3 (Recommended
Practices), and 1212 (CSR architecture). Digital AXP platforms implement
Profile B, which is intended as a general purpose I/O bus. Futurebus+ Profile
B is required to support 32 bit addressing (A32) and optionally supports 64 bit
addressing (A64). Data widths from 32 to 256 bits are supported, though only
32 bit support (D32) is required. The bus uses an asynchronous protocol, so that
the achievable bandwidth depends on the components used to build the modules.
Current implementations (DEC 4000 and DEC 10000/7000) have demonstrated
bandwidths on the order of 150 MB/second.
The Futurebus+ specifications describe a module as occupying a physical
backplane slot. A module can implement one or two nodes. A maximum of 62
nodes per bus is supported. The physical backplane slot number of a module
determines the base address of Futurebus+ node space for the nodes on the
module. Futurebus+ is currently available on the DEC 10000/7000 and DEC 4000
platforms.
15.2 Futurebus+ Address Space
The Futurebus+ supports 2 distinct address spaces, 32 bit address space (A32)
and 64 bit address space (A64). Since all nodes are required to support A32,
all A64 transactions to addresses with 32 bit equivalents should use A32 to
insure interoperability . 32 bit and 64 bit Futurebus+ address space is shown in
Figure 15–1.
15–1