Specifications

Futurebus+ Bus Support
15.7 Futurebus+ Interrupts
Figure 15–5 Futurebus+ Target Register
Host System
Fbus
Bridge
Fbus
Interrupt Request
registers implemented
on Fbus Bridge
Fbus Adapter
Interrupt Target
Interrupt Vector
Interrupt Target programmed with Interrupt Request
register address during driver initialization.
Interrupt Vector programmed with vector during driver
initialization.
Fbus Adapter interrupts host by writing Interrupt Vector
contents to Interrupt Request register on bridge.
ZK−6730A−GE
The Futurebus+ Bridge supplies different Interrupt Request register addresses to
allow Futurebus+ adapters to interrupt the host at different Interrupt Priority
Levels. On the DEC 10000/7000 and DEC 4000 platforms, the Interrupt Request
register addresses are used as follows:
Interrupt Register oDEC 10000/7000 DEC 4000
800 IPL 14 (hex) interIPL 14 (hex) interrupt
804 IPL 15 (hex) interIPL 14 (hex) interrupt
808 IPL 16 (hex) interIPL 14 (hex) interrupt
80C IPL 17 (hex) interIPL 14 (hex) interrupt
The actual address of the bridge Interrupt Register depends on the Futurebus+
node number of the bridge. The bridge may reside in different Futurebus+ slots
on different platforms, so OpenVMS AXP uses system routine IOC$NODE_DATA
to return the base Interrupt Register address to a driver. An example call to
IOC$NODE_DATA to get the base Interrupt Register address is shown below:
status = ioc$node_data (crb_address,
ioc$k_fbus_int_loc,
addr_of_longword);
IOC$NODE_DATA finds the bridge Futurebus+ slot number and returns
bridge_nodespace_base + 800
in the caller’s buffer. If the bridge is installed in Futurebus+ slot 0, for example,
IOC$NODE_DATA would return FFFC0800 to the caller. The driver should
program this value (if interrupt priority level 14H is desired) to the Interrupt
Target register on the driver’s Futurebus+ adapter.
15–7