User`s guide

ManualsBrandsVax ManualsHousehold AppliancesV-044B Series

VAX 4000

Model 100, 100A, 105A, 106A

KA52/53/54 CPU System Maintenance

Order Number: EK–473AB–MG. C01

September 1995

This manual gives maintenance information for systems that use the KA52,

KA53, or KA54 CPU module.

Digital Equipment Corporation

Maynard, Massachusetts

Summary of content (272 pages)

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VAX 4000 Model 100, 100A, 105A, 106A KA52/53/54 CPU System Maintenance Order Number: EK–473AB–MG. C01 September 1995 This manual gives maintenance information for systems that use the KA52, KA53, or KA54 CPU module.
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First Printing, August 1994 Revised September 1995 Digital Equipment Corporation makes no representations that the use of its products in the manner described in this publication will not infringe on existing or future patent rights, nor do the descriptions contained in this publication imply the granting of licenses to make, use, or sell equipment or software in accordance with the description. © Digital Equipment Corporation 1994, 1995. All Rights Reserved.
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Contents Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii 1 KA52/53/54 CPU Module Description 1.1 1.1.1 1.1.2 1.2 1.3 1.4 KA52/53/54 CPU Module . . . . . . . . . . . . . . . . Physical Description . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . MS44 and MS44L Memory Modules . . . . . . . MS44 or MS44L Memory Option Installation Memory Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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3 KA52/53/54 Firmware Commands 3.1 Console I/O Mode Control Characters . . . . . . . . . 3.1.1 Command Syntax . . . . . . . . . . . . . . . . . . . . . . 3.1.2 Address Specifiers . . . . . . . . . . . . . . . . . . . . . 3.1.3 Symbolic Addresses . . . . . . . . . . . . . . . . . . . . 3.1.4 Console Numeric Expression Radix Specifiers 3.1.5 Console Command Qualifiers . . . . . . . . . . . . . 3.1.6 Console Command Keywords . . . . . . . . . . . . . 3.2 Console Commands . . . . . . . . . . . . . . . . . . . .
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4.5 Machine State on Power-Up . . . . . . . . . . . . . . . . . . . . . . . 4.6 Main Memory Layout and State . . . . . . . . . . . . . . . . . . . 4.6.1 Reserved Main Memory . . . . . . . . . . . . . . . . . . . . . . . 4.6.1.1 PFN Bitmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.1.2 Scatter/Gather Map . . . . . . . . . . . . . . . . . . . . . . . 4.6.1.3 Firmware "Scratch Memory" . . . . . . . . . . . . . . . . 4.6.2 Contents of Main Memory . . . . . . . . . . . . . . . . . . . . . 4.6.
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5.2.10 Repair Data for Returning FRUs . . . . . . . . . . . . . . . . . . . 5.3 Power-On Self-Test (POST) and ROM-Based Diagnostic (RBD) Failures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.1 FE Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.2 Overriding Halt Protection . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.3 Isolating Memory Failures . . . . . . . . . . . . . . . . . . . . . . . . . 5.
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B.1.2 B.1.2.1 B.1.2.2 B.1.2.3 B.1.3 Call-Back Entry Points . . . . . . . . CP$GETCHAR_R4 . . . . . . . . . CP$MSG_OUT_NOLF_R4 . . . CP$READ_WTH_PRMPT_R4 Boot Information Pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–4 B–5 B–6 B–6 B–7 Halt Dispatch State Machine . . . . . . . . . . . . . . . . . . . .
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H Related Documents Glossary Index Examples 1–1 1–2 4–1 4–2 4–3 4–4 5–1 5–2 5–3 5–4 5–5 5–6 5–7 5–8 5–9 5–10 5–11 5–12 5–13 5–14 5–15 5–16 5–17 5–18 5–19 viii Successful Running of Memory Test Script A8 . . . . . . . . . . . . Typical Failure After Running Memory Test Script A8 . . . . . Language Selection Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . Successful Diagnostic Countdown . . . . . . . . . . . . . . . . . . . . . Successful Power-Up to List of Bootable Devices . . . . . . . . . .
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6–1 6–2 FEPROM Update via Ethernet . . . . . . . . . . . . . . . . . . . . . . . FEPROM Update via Tape . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5 6–7 Figures 1–1 1–2 1–3 1–4 1–5 2–1 4–1 4–2 4–3 4–4 4–5 4–6 5–1 5–2 5–3 5–4 5–5 5–6 5–7 5–8 5–9 6–1 6–2 B–1 B–2 B–3 B–4 E–1 E–2 E–3 E–4 KA52/53/54 CPU Module . . . . . . . . . . . . . . . . . . . . . . . . . KA52/53/54 CPU Module Block Diagram . . . . . . . . . . . . . KA52/53/54 Controls, Indicators, Ports, and Connectors .
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Tables 1–1 1–2 2–1 2–2 2–3 2–4 3–1 3–2 3–3 3–4 3–5 3–6 4–1 4–2 4–3 4–4 4–5 5–1 5–2 5–3 5–4 5–5 A–1 A–2 B–1 B–2 B–3 C–1 C–2 C–3 E–1 E–2 E–3 F–1 x Functions of Controls, Indicators, Connectors . . . . . . . . KA52/53/54 CPU Module Memory Configurations . . . . . KA52/53/54 Internal Mass Storage Devices . . . . . . . . . . Supported Asynchronous Communications Options . . . . Supported Synchronous Communications Options . . . . . DSW41-AA and DSW42-AA Communications Support . . Console Symbolic Addresses . .
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G–1 G–2 G–3 HALT Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VMB Error Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Console Error Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Preface This manual describes the KA52 CPU module used in the VAX 4000 Model 100 and 100A systems, the KA53 CPU module used in the VAX 4000 Model 105A system, and the KA54 CPU module used in the VAX 4000 Model 106A system. It provides the configuration guidelines, ROM-based diagnostic information, and troubleshooting information for systems containing the KA52/53/54 CPU modules.
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xiv • Appendix A gives the address assignments. • Appendix B describes ROM partitioning and subroutine entry points. • Appendix C gives definitions of the key global data structures used by the CPU firmware. • Appendix D gives the normal state of all configurable bits in the CPU module as they are left after the successful completion of power-up ROM diagnostics. • Appendix E describes how the CPU firmware partitions the SCC 1 KB battery-backed-up (BBU) RAM. • Appendix F gives MOP counters.
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Conventions The following conventions are used in this manual: Convention Description Ctrl/x Ctrl/x indicates that you hold down the Ctrl key while you press another key or mouse button (indicated here by x). x A lowercase italic x indicates the generic use of a letter. For example, xxx indicates any combination of three alphabetic characters. n A lowercase italic n indicates the generic use of a number. For example, 19nn indicates a 4-digit number in which the last 2 digits are unknown.
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xvi Convention Description Radix indicators The radix of a number is written as a word enclosed in parentheses, for example, 23(decimal) or 34(hexadecimal). >>> Three right angle brackets indicate the console prompt. UPPERCASE A word in uppercase indicates a command. Note A note contains information that is of special importance to the user. Caution A caution contains information to prevent damage to the equipment. Warning A warning contains information to prevent personal injury.
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1 KA52/53/54 CPU Module Description This chapter describes the KA52 central processing unit (CPU) module that is used in the VAX 4000 Model 100 and 100A systems, the KA53 CPU module that is used in the VAX 4000 Model 105A systems and the KA54 CPU module that is used in the VAX 4000 Model 106A.
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KA52/53/54 CPU Module Description 1.1 KA52/53/54 CPU Module 1.1.1 Physical Description The KA52/53/54 CPU module is the primary component of the VAX 4000 system in which it is installed. The KA52/53/54 CPU module contains the following components: • The NVAX processor chip—This chip is a complementary metal oxide semiconductor (CMOS) virtual memory microprocessor.
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KA52/53/54 CPU Module Description 1.
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KA52/53/54 CPU Module Description 1.
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KA52/53/54 CPU Module Description 1.
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KA52/53/54 CPU Module Description 1.
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KA52/53/54 CPU Module Description 1.1 KA52/53/54 CPU Module Table 1–1 (Cont.) Functions of Controls, Indicators, Connectors Component Description Internal SCSI connector A connector that provides a connection for SCSI devices mounted inside the system enclosure. Basic system memory connectors Four connectors for the basic system memory modules. Memory expansion connectors Four connectors for an additional memory option.
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KA52/53/54 CPU Module Description 1.1 KA52/53/54 CPU Module Table 1–1 (Cont.) Functions of Controls, Indicators, Connectors Component Break/Enable switch Description 1 A two-position switch that determines the function of MMJ port 3 as follows: • Up position—MMJ port 3 functions as a console port. In this state, you can press the Break key on the keyboard of a terminal connected to MMJ port 3 to put the system in console mode. • Down position—MMJ port 3 functions as a normal communications port.
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KA52/53/54 CPU Module Description 1.2 MS44 and MS44L Memory Modules 1.2 MS44 and MS44L Memory Modules The MS44 and the MS44L memory modules provide memory expansion for the KA52/53/54 CPU module.
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KA52/53/54 CPU Module Description 1.2 MS44 and MS44L Memory Modules Figure 1–4 Memory Expansion Connectors 0A 1E 0C 1G 0B 1F 0D 1H Note: 0A 0B 0C and 0D are identifiers for the basic system memory connectors. GA_EN00083A_92A Table 1–2 KA52/53/54 CPU Module Memory Configurations Total Memory Increment 11 Increment 2 (0A + 0B + 0C + 0D)2 (1E + 1F + 1G + 1H)2 (bytes) 16M MS44L-BC 32M MS44L-BC 64M MS44-DC 80M MS44-DC MS44L-BC 128M MS44-DC MS44-DC 1 Basic 2 0A, MS44L-BC system memory.
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KA52/53/54 CPU Module Description 1.3 MS44 or MS44L Memory Option Installation 1.3 MS44 or MS44L Memory Option Installation The MS44 and MS44L memory options consist of four memory modules each. Install an MS44 or MS44L memory option on the KA52/53/54 CPU module as follows: 1. Position the KA52/53/54 CPU module, component side up, so that the edge connectors are facing away from you. 2.
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KA52/53/54 CPU Module Description 1.3 MS44 or MS44L Memory Option Installation Figure 1–5 Memory Module Installation GA_EN00084A_92A 4. Tilt the memory module toward the front of the enclosure until the metal locking clips on the connector lock the memory module in position. 5. Repeat the procedure in step 1 for the subsequent memory modules. Insert them into the other connectors in the set on the KA52/53/54 CPU module. 6. Run the MEM diagnostic test, refer to Section 1.
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KA52/53/54 CPU Module Description 1.3 MS44 or MS44L Memory Option Installation 1.4 Memory Tests The memory tests check the system memory contained on the MS44 and/or MS44L memories. The tests run automatically as part of the power-up tests and initialization, when you turn on the system. The memory tests are a group of individual tests which can be called individually or normally as a group under a specific script number.
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KA52/53/54 CPU Module Description 1.4 Memory Tests The failure is reported by the count bad pages test 40 at end of the script. Issuing the SHOW MEMORY command shows which memory set caused the failure. Bad pages were detected in memory set 0.
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KA52/53/54 CPU Module Description 1.4 Memory Tests Test 4D - Address Uniqueness Test The main purpose of the test is to verify that each set on each board can be uniquely addressed. The test writes a unique pattern to each location to be tested then verifies all locations. Test 4C - MEMORY ECC, Verify Error Detection and Reporting The main purpose of this test is to test ECC logic. It is not intended to test the memory RAMs explicitly.
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KA52/53/54 CPU Module Description 1.4 Memory Tests Test 40 - MEMORY Count Bad Pages Marked in Bitmap This test is normally run last in a script of memory tests. Its only purpose is to read the bitmap when done and check to see if any pages in memory were marked bad, if so, report an error. Note If this test fails, do SHOW MEMORY to see which set has bad pages in it.
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2 Configuration This chapter describes the KA52/53/54 system configurations. It gives information on the following: • Memory configurations • Mass storage devices • Communications options 2.1 Memory Configurations A KA52/53/54 system has a basic memory of 16M bytes or 64M bytes. This consists of four MS44L-AA memory modules or four MS44-CA memory modules. You can add memory in 16M byte or 64M byte increments, up to a maximum of 128M bytes. See Section 1.2 for information on the memory configurations.
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Configuration 2.2 Mass Storage Devices 2.2.1 Internal Mass Storage Devices Table 2–1 shows some of the internal mass storage devices that a KA52/53/54 system supports. Table 2–1 KA52/53/54 Internal Mass Storage Devices Option Name Description Size1 Capacity (in) RF31T Disk drive 3.5 381 Mbytes RF35 Disk drive 3.5 852 Mbytes RF36 Disk drive 3.5 1.6 Gbytes RZ23L Disk drive 3.5 120-MB RZ24 Disk drive 3.5 209-MB RZ24L Disk drive 3.5 245-MB RZ25 Disk drive 3.
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Configuration 2.2 Mass Storage Devices The system enclosure determines the combinations of internal mass storage devices in a KA52/53/54 system. See the VAX 4000 BA42B Enclosure Maintenance manual for more information. 2.2.2 External Mass Storage Devices The external mass storage devices connect to KA52/53/54 systems through either the DSSI or the SCSI connector on the back of the system enclosure. In KA52/53/54 systems, the SCSI bus supports a maximum of seven mass storage devices.
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Configuration 2.2 Mass Storage Devices Figure 2–1 SZ Expansion Box Numbering System SZ 1 n x − x x Enclosure Type Power Cord Type 2 = BA42 Enclosure 6 = BA46 Enclosure A = 120 V ac B = 240 V ac Left Compartment Right Compartment A = RZ55 B = RZ56 C = RZ57 P = RZ25 1 R = RZ58 X = Empty A = RZ55 B = RZ56 C = RZ57 D = TLZ04 2 E = TZK10 F = RRD42 H = TZ30 L = RX23 M = RX33 P = RZ25 1 R = RZ58 X = Empty 1 2 − The RZ25 disk drive fits in the BA42 enclosure only.
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Configuration 2.2 Mass Storage Devices • Terminate the SCSI and DSSI buses correctly. Failure to do this can cause a system failure or corrupt data. • Digital recommends that you connect all SCSI and DSSI devices to the same ac power source. • Do not add or remove devices that are connected to the SCSI or DSSI buses while the power is on.
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Configuration 2.2 Mass Storage Devices 2.2.6 SCSI ID Numbers Each mass storage device must have a unique SCSI ID number. SCSI ID 6 is typically used for the SCSI controller. 2.2.7 DSSI ID Numbers Each mass storage device must have a unique DSSI ID number. DSSI ID 6 or 7 is typically used for the DSSI controller. 2.
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Configuration 2.3 Communications Options Table 2–3 Supported Synchronous Communications Options Option Description Model 100 DSW42-AA1 1 This Two-line EIA-232/V.24 synchronous option with two external cables, BC19D-02 (17-01110-01) option is supplied with two external cables that support the EIA-232/V.24 interface. The DSW41-AA and the DSW42-AA options also support the communications interfaces listed in Table 2–4, but you must order the external cables separately.
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3 KA52/53/54 Firmware Commands This chapter describes the console mode control characters, the command syntax, the command modifiers, and all of the console commands. You can enter these commands when the system is in console mode. Console mode is indicated when the console prompt (>>>) is displayed.
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KA52/53/54 Firmware Commands 3.1 Console I/O Mode Control Characters
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KA52/53/54 Firmware Commands 3.1 Console I/O Mode Control Characters CTRL/C Echoes ^C and aborts processing of a command. When entered as part of a command line, deletes the line. CTRL/O Ignores transmissions to the console terminal until the next CTRL/O is entered. Echoes ^O when disabling output, not echoed when it re-enables output. Output is re-enabled if the console prints an error message, or if it prompts for a command from the terminal.
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KA52/53/54 Firmware Commands 3.1 Console I/O Mode Control Characters 3.1.3 Symbolic Addresses The console supports symbolic references to addresses. A symbolic reference defines the address space and the offset into that space. Table 3–1 lists symbolic references supported by the console, grouped according to address space. You do not have to use an address space qualifier when using a symbolic address.
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KA52/53/54 Firmware Commands 3.1 Console I/O Mode Control Characters Table 3–1 (Cont.
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KA52/53/54 Firmware Commands 3.1 Console I/O Mode Control Characters Table 3–1 (Cont.
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KA52/53/54 Firmware Commands 3.1 Console I/O Mode Control Characters Table 3–1 (Cont.
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KA52/53/54 Firmware Commands 3.1 Console I/O Mode Control Characters 3.1.4 Console Numeric Expression Radix Specifiers By default, the console treats any numeric expression used as an address or a datum as a hexadecimal integer. The user may override the default radix by using one of the specifiers listed in Table 3–3.
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KA52/53/54 Firmware Commands 3.1 Console I/O Mode Control Characters Table 3–4 (Cont.) Console Command Qualifiers Qualifier Description Data Control /STEP:{size} Step. Overrides the default increment of the console current reference. Commands that manipulate memory, such as EXAMINE, DEPOSIT, MOVE, and SEARCH, normally increment the console current reference by the size of the data being used. /WRONG Wrong. On writes, 3 is used as the value of the ECC bits, which always generates double bit errors.
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KA52/53/54 Firmware Commands 3.1 Console I/O Mode Control Characters Table 3–5 Command Keywords by Type Processor Control Data Transfer Console Control BOOT DEPOSIT CONFIGURE CONTINUE EXAMINE FIND HALT MOVE REPEAT INITIALIZE SEARCH SET NEXT X SHOW START TEST LOGIN UNJAM ! Table 3–6 Console Command Summary Command Qualifiers Argument Other(s) BOOT /R5:{boot_flags} /{boot_flags} [{boot_device}[,{boot_ device}]...
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KA52/53/54 Firmware Commands 3.1 Console I/O Mode Control Characters Table 3–6 (Cont.) Console Command Summary Command Qualifiers Argument Other(s) MOVE /B /W /L /Q — /V /P /U /N:{count} /STEP:{size} /WRONG {src_address} {dest_ address} NEXT — [{count}] — REPEAT — {command} — SEARCH /B /W /L /Q — /V /P /U /N:{count} /STEP:{size} /WRONG /NOT {start_address} {pattern} [{mask}] SET BFLAG — {bitmap} — SET BOOT — [{boot_device}[,{boot_ device}]...
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KA52/53/54 Firmware Commands 3.1 Console I/O Mode Control Characters Table 3–6 (Cont.) Console Command Summary Command Qualifiers Argument Other(s) SHOW RLV12 — — — SHOW SCSI — — — SHOW TRANSLATION {phys_address} — SHOW UQSSP — — — SHOW VERSION — — — START — {address} — TEST — {test_number} [{parameters}] UNJAM — — — X — {address} {count} 3.
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KA52/53/54 Firmware Commands 3.2 Console Commands continuously attempt to boot from EZA0. Set the default boot device and boot flags with the SET BOOT and SET BFLAG commands. If you do not set a default boot device, the processor times out after 30 seconds and attempts to boot from the Ethernet device, EZA0. Qualifiers: Command specific: /R5:{boot_flags} A 32-bit hex value passed to VMB in R5. The console does not interpret this value. Use the SET BFLAG command to specify a default boot flags longword.
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KA52/53/54 Firmware Commands 3.2 Console Commands Example: >>>CONTINUE $ !OpenVMS DCL prompt 3.2.3 DEPOSIT The DEPOSIT command deposits data into the address specified. If you do not specify an address space or data size qualifier, the console uses the last address space and data size used in a DEPOSIT, EXAMINE, MOVE, or SEARCH command. After processor initialization, the default address space is physical memory and the default data size is longword.
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KA52/53/54 Firmware Commands 3.2 Console Commands 3.2.4 EXAMINE The EXAMINE command examines the contents of the memory location or register specified by the address. If no address is specified, + is assumed. The display line consists of a single character address specifier, the physical address to be examined, and the examined data. EXAMINE uses the same qualifiers as DEPOSIT. However, the /WRONG qualifier causes EXAMINE to ignore ECC errors on reads from physical memory.
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KA52/53/54 Firmware Commands 3.2 Console Commands >>>E/P 0 P 00000000 00000000 ! Examine local memory 0. >>>EX /INS 20040000 P 20040000 11 BRB ! Examine 1st byte of ROM. 20040019 >>>EX /INS/N:5 P 20040019 P 20040024 P 2004002F P 20040036 P 2004003D P 20040044 20040019 D0 MOVL D2 MCOML D2 MCOML 7D MOVQ D0 MOVL DB MFPR ! Disassemble from branch.
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KA52/53/54 Firmware Commands 3.2 Console Commands >>>EX SP G 0000000E 00000000 >>>FIND /MEM >>>EX SP G 0000000E 00000200 >>>FIND /RPB ?2C FND ERR 00C00004 >>> ! Check the SP. ! Look for a valid 128 Kbytes. ! Note where it was found. ! Check for valid RPB. ! None to be found here. 3.2.6 HALT The HALT command has no effect. It is included for compatibility with other VAX consoles. Format: HALT Example: >>>HALT >>> ! Pretend to halt. 3.2.
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KA52/53/54 Firmware Commands 3.2 Console Commands Valid commands: BOOT [[/R5:]] [] CONFIGURE CONTINUE DEPOSIT []
[...] EXAMINE [] [
] FIND [/MEMORY | /RPB] HALT HELP INITIALIZE LOGIN MOVE []

NEXT [] REPEAT SEARCH []
[] SET BFLG SET BOOT SET HALT <0..
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KA52/53/54 Firmware Commands 3.2 Console Commands >>> 3.2.8 INITIALIZE The INITIALIZE command performs a processor initialization. Format: INITIALIZE The following registers are initialized: Register State at Initialization PSL 041F0000 IPL 1F ASTLVL 4 SISR 0 ICCS Bits <6> and <0> clear; the rest are unpredictable.
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KA52/53/54 Firmware Commands 3.2 Console Commands Example: >>>INIT >>> 3.2.9 LOGIN Allows you to put the system in privileged console mode. When the console security feature is enabled and when you put the system in secure console mode, the system operates in unprivileged console mode. You can access only a subset of the console commands. To access the full range of console commands, you must use this command. This command may only be executed in secure console mode.
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KA52/53/54 Firmware Commands 3.2 Console Commands Qualifiers: Data control: /B, /W, /L, /Q, /N:{count}, /STEP:{size}, /WRONG Address space control: /V, /U, /P Arguments: {src_address} A longword address that specifies the first location of the source data to be copied. {dest_address} A longword address that specifies the destination of the first byte of data. These addresses may be an actual address or a symbolic address. If no address is specified, + is assumed.
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KA52/53/54 Firmware Commands 3.2 Console Commands The console enters the "Spacebar Step Mode". In this mode, subsequent spacebar strokes initiate single steps and a carriage return forces a return to the console prompt. The following restrictions apply: • If memory management is enabled, the NEXT command works only if the first page in SSC RAM is mapped in S0 (system) space. • Overhead associated with the NEXT command affects execution time of an instruction.
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KA52/53/54 Firmware Commands 3.2 Console Commands P 00001007 P 00001002 P 00001004 P 00001007 P 00001009 >>>N P 00001009 >>> 12 D6 D1 12 11 BNEQ INCL CMPL BNEQ BRB 11 BRB 00001002 R0 S^#05,R0 00001002 00001009 00001009 3.2.12 REPEAT The REPEAT command repeatedly displays and executes the specified command. Press Ctrl/C to stop the command. You can specify any valid console command except the REPEAT command. Format: REPEAT {command} Arguments: {command} A valid console command other than REPEAT.
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KA52/53/54 Firmware Commands 3.2 Console Commands 3.2.13 SEARCH The SEARCH command finds all occurrences of a pattern and reports the addresses where the pattern was found. If the /NOT qualifier is present, the command reports all addresses in which the pattern did not match. Format: SEARCH [qualifier-list] {address} {pattern} [{mask}] SEARCH accepts an optional mask that indicates bits to be ignored (don’t care bits). For example, to ignore bit 0 in the comparison, specify a mask of 1.
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KA52/53/54 Firmware Commands 3.2 Console Commands {pattern} The target data. [{mask}] A mask of the bits desired in the comparison.
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KA52/53/54 Firmware Commands 3.2 Console Commands BOOT Sets the default boot device. The value must be a valid device name or list of device names as specified in the BOOT command description in Section 3.2.1. HALT Sets the user-defined halt action. Acceptable values are the keywords "default", "restart", "reboot", "halt", "restart_reboot", or a number in the range 0 to 4 inclusive. HOST Invoke the DUP or MAINTENANCE driver on the selected node. Only SET HOST/DUP accepts a value parameter.
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KA52/53/54 Firmware Commands 3.2 Console Commands 3.2.15 SHOW The SHOW command displays the console parameter you specify. Format: SHOW {parameter} Parameters: BFLAG Displays the default R5 boot flags. BOOT Displays the default boot device. CONFIG Displays the system configuration. The command displays information about the devices that the firmware has tested. It also displays the device errors that the most recent device test detected. DEVICE Displays all devices in the system.
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KA52/53/54 Firmware Commands 3.2 Console Commands QBUS Displays all Q22–bus I/O addresses that respond to an aligned word read, and speculative device name information. For each address, the console displays the address in the VAX I/O space in hex, the address as it would appear in the Q22–bus I/O space in octal, and the word data that was read in hex. This command may take several minutes to complete. Press Ctrl/C to terminate the command. During execution, the command disables the scatter-gather map.
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KA52/53/54 Firmware Commands 3.
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KA52/53/54 Firmware Commands 3.2 Console Commands >>>SHOW SCSI SCSI Adapter 0 (761300), SCSI ID 7 -DKA100 (DEC TLZ04) >>> >>>SHOW TRANSLATION 1000 V 80001000 >>> >>>SHOW VERSION KA52 Vn.n VMBn.n >>> >>>show dssi DSSI Bus 0 Node 1 (R5WBAA) -DIA1 (RF35) DSSI Bus 0 Node 6 (KF72PB) DSSI Bus 0 Node 7 (*) 3.2.16 START The START command starts instruction execution at the address you specify. If no address is given, the current PC is used.
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KA52/53/54 Firmware Commands 3.2 Console Commands Arguments: {test_number} A two-digit hex number specifying the test to be executed. No meaning to console, but meaning to tests themselves. T 9E lists arguments used by applicable tests. {test_arguments} Up to five additional test arguments. These arguments are accepted, but they have no meaning to the console. Example: >>>TEST 0 72..71..70..69..68..67..66..65..64..63..62..61..60..59..58..57.. 56..55..54..53..52..51..50..49..48..47..46..45..44..43..42..
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KA52/53/54 Firmware Commands 3.
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KA52/53/54 Firmware Commands 3.
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KA52/53/54 Firmware Commands 3.2 Console Commands 3.2.18 UNJAM The UNJAM command performs an I/O bus reset, by writing a 1 (one) to IPR 55 (decimal). SHAC and SGEC are explicitly reset, EDAL_INTREQ register error bits are cleared and SCSI_DMA map registers are cleared. Format: UNJAM Example: >>>UNJAM >>> 3.2.19 X—Binary Load and Unload The X command is for use by automatic systems communicating with the console.
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KA52/53/54 Firmware Commands 3.2 Console Commands into an 8-bit register initially set to zero. If the final content of the register is nonzero, the data or checksum are in error, and the console responds with an error message. If the command is a binary unload (bit 31 of the count is set), the console responds with the input prompt (>>>), followed by the specified number of bytes of binary data. As each byte is sent, it is added to a checksum register initially set to zero.
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KA52/53/54 Firmware Commands 3.2 Console Commands 3.2.20 ! (Comment) The comment character (an exclamation point) is used to document command sequences. It can appear anywhere on the command line. All characters following the comment character are ignored. Format: ! Example: >>>! The console ignores this line.
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4 System Initialization and Acceptance Testing (Normal Operation) This chapter describes the system initialization, testing, and bootstrap processes that occur at power-up. In addition, the acceptance test procedure to be performed when installing a system or whenever adding or replacing FRUs is described. 4.1 Basic Initialization Flow On power-up, the firmware identifies the console device, optionally performs a language inquiry, and runs the diagnostics.
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System Initialization and Acceptance Testing (Normal Operation) 4.1 Basic Initialization Flow Loading system software. Failure. Restarting system software. Performing normal system tests. Tests completed. Normal operation not possible. Bootfile. Memory configuration error. No default boot device has been specified. Available devices. Device? Retrying network bootstrap. The position of the Break Enable/Disable switch has no effect on these conditions.
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System Initialization and Acceptance Testing (Normal Operation) 4.1 Basic Initialization Flow Following a successful diagnostic countdown (see Example 4–2), the console may prompt you for a default boot device. Example 4–2 Successful Diagnostic Countdown KA52-A VX.X, VMB 2.14 Performing normal system tests. 72..71..70..69..68..67..66..65..64..63..62..61..60..59..58..57.. 56..55..54..53..52..51..50..49..48..47..46..45..44..43..42..41.. 40..39..38..37..36..35..34..33..32..31..30..29..28..27..26..25.. 24..23..
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System Initialization and Acceptance Testing (Normal Operation) 4.2 Power-On Self-Tests (POST) Figure 4–1 Console Banner KA52-A V n.n, VMB n.n minor release of VMB major release of VMB minor release of firmware major release of firmware type of release: X - engineering release T - field test release V - volume release processor type MLO-009883 4. Displays language inquiry menu on console if console supports multinational character set (MCS) and any of the following are true: • Battery is dead.
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System Initialization and Acceptance Testing (Normal Operation) 4.
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System Initialization and Acceptance Testing (Normal Operation) 4.2 Power-On Self-Tests (POST) Example 4–3 Successful Power-Up to List of Bootable Devices KA52-A VX.X, VMB 2.14 Performing normal system tests. 72..71..70..69..68..67..66..65..64..63..62..61..60..59..58..57.. 56..55..54..53..52..51..50..49..48..47..46..45..44..43..42..41.. 40..39..38..37..36..35..34..33..32..31..30..29..28..27..26..25.. 24..23..22..21..20..19..18..17..16..15..14..13..12..11..10..09.. 08..07..06..05..04..03.. Tests completed.
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System Initialization and Acceptance Testing (Normal Operation) 4.2 Power-On Self-Tests (POST) The following modules have one green LED, which indicates that the module is receiving +5 and +12 Vdc and has passed self-tests: CXA16 CXB16 CXY08 4.2.3 Power-Up Tests for Mass Storage Devices An RF-series ISE may fail either during initial power-up or during normal operation. In both cases, the failure is indicated by the lighting of the red fault LED on the drive’s front panel.
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System Initialization and Acceptance Testing (Normal Operation) 4.3 CPU ROM-Based Diagnostics The diagnostics run automatically on power-up. While the diagnostics are running, the LED displays a hexadecimal number; while booting the operating system, 2 through 0 display. The ROM-based diagnostics are a collection of individual tests with parameters that you can specify. A data structure called a script points to the tests (see Section 4.3.2). There are several field and manufacturing scripts.
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System Initialization and Acceptance Testing (Normal Operation) 4.
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System Initialization and Acceptance Testing (Normal Operation) 4.3 CPU ROM-Based Diagnostics Example 4–4 (Cont.
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System Initialization and Acceptance Testing (Normal Operation) 4.3 CPU ROM-Based Diagnostics User Determined Parameters Parameters that you can specify are written out, as shown in the following examples: 30 2005C33C Memory_Init_Bitmap *** mark_Hard_SBEs ****** 54 20055181 Virtual_Mode ********* For example, the virtual mode test contains several parameters, but you cannot specify any that appear in the table as asterisks.
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System Initialization and Acceptance Testing (Normal Operation) 4.3 CPU ROM-Based Diagnostics to avoid corrupting these data structures. The location of the maps is displayed using the SHOW MEMORY/FULL command. 4.3.2 Scripts Most of the tests shown by utility 9E are arranged into scripts. A script is a data structure that points to various tests and defines the order in which they are run.
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System Initialization and Acceptance Testing (Normal Operation) 4.3 CPU ROM-Based Diagnostics Table 4–2 Scripts Available to Customer Services Script1 Enter with TEST Command Description A0 A0 Runs user-defined script. Enter T 9F to create. A1 A1, 0 Primary power-up script; builds memory bitmap; marks hard single-bit errors and multi-bit errors. Continues on error. A3 A3, A4 Runs power-up tests, halts on first error. A4 A4 Loops on A3. Press Ctrl C to exit.
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System Initialization and Acceptance Testing (Normal Operation) 4.4 Basic Acceptance Test Procedure 4.4 Basic Acceptance Test Procedure Perform the acceptance testing procedure listed below, after installing a system, or whenever adding or replacing the following: CPU module MS44 memory SIMM DSSI device SCSI device SYNC device ASYNC device 1.
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System Initialization and Acceptance Testing (Normal Operation) 4.4 Basic Acceptance Test Procedure Examine MEMCON 0–1 to verify the memory configuration. Each pair of MEMCONs maps one memory module as follows: MEMCON0 Set 0; 0A, 0B, 0C, 0D MEMCON1 Set 1; 1E, 1F, 1G, 1H 2.
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System Initialization and Acceptance Testing (Normal Operation) 4.4 Basic Acceptance Test Procedure Checks the Q22–bus interrupt logic Note Test 81 does not test the KFQSA option card. If you do not specify the CSR address, the test searches for and runs on the first MSCP device by default. To test the first TMSCP device, you must specify the first parameter: >>>T 81 20001940 You can specify other addresses if you have multiple MSCP or TMSCP devices.
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System Initialization and Acceptance Testing (Normal Operation) 4.4 Basic Acceptance Test Procedure 4. Run one pass of the DSSI internal drive tests (DRVTST and DRVEXR) using the Diagnostic Utility Protocol (DUP) driver as described in Section 5.4. 5. If the above steps complete successfully and you have time to test the Q–bus options, load MDM. (MDM release 137A, V4.8A, or higher is required for VAX 4000 Model 100/100A systems; Model 105A/106A requires release 138, V4.9, or higher.
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System Initialization and Acceptance Testing (Normal Operation) 4.6 Main Memory Layout and State Figure 4–2 Memory Layout After Power-Up Diagnostics 0 . . . . Available system memory (pages potentially good or bad) . . . . PFN bitmap PFN bitmap (always on page boundary and size in pages n = (# of MB )/2) n pages Firmware "scratch memory" (always 16 KB) 32 pages Q22-Bus Scatter/Gather Map (always on 32 KB boundary) 64 pages QMR base . Potential "bad" memory . Top of Memory MLO-008454 4.6.
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System Initialization and Acceptance Testing (Normal Operation) 4.6 Main Memory Layout and State Each bit in the PFN bitmap corresponds to a page in main memory. There is a one to one correspondence between a page frame number (origin 0) and a bit index in the bitmap. A one in the bitmap indicates that the page is "good" and can be used. A zero indicates that the page is "bad" and should not be used. The PFN bitmap is protected by a checksum stored in the NVRAM.
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System Initialization and Acceptance Testing (Normal Operation) 4.6 Main Memory Layout and State 4.6.3 Memory Controller Registers The CPU firmware assigns bank numbers to the MEMCONn registers in ascending order, without attempting to disable physical banks that contain errors. High order unused banks are set to zero. Error loggers should capture the following bits from each MEMCONn register: • MEMCONn <31> (bank enable bit).
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System Initialization and Acceptance Testing (Normal Operation) 4.7 Operating System Bootstrap 4.7.1 Preparing for the Bootstrap Prior to dispatching to the primary bootstrap (VMB), the firmware initializes the system to a known state. The initialization sequence follows: 1. Check the console program mailbox "bootstrap in progress" bit (CPMBX<2>(BIP)). If it is set, bootstrap fails. 2. If this is an automatic bootstrap, display the message "Loading system software." on the console terminal. 3.
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System Initialization and Acceptance Testing (Normal Operation) 4.7 Operating System Bootstrap R0 Address of descriptor of boot device name; 0 if none specified R2 Length of PFN bitmap in bytes R3 Address of PFN bitmap R4 Time-of-day of bootstrap from PR$_TODR R5 Boot flags R10 Halt PC value R11 Halt PSL value (without halt code and map enable) AP Halt code SP Base of 128-Kbyte good memory block + 512 PC Base of 128-Kbyte good memory block + 512 R1, R6, R7, R8, R9, FP 0 10.
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System Initialization and Acceptance Testing (Normal Operation) 4.7 Operating System Bootstrap Figure 4–3 Memory Layout Prior to VMB Entry 0 . Potential "bad" memory . Base Reserved for RPB, initial stack Base+512(SP,PC) 256 pages for VMB 128 KB block of "good" memory (page aligned) VMB image Balance of 128 KB block to be used for SCB, stack, and the secondary bootstrap. . . . Unused memory . . .
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System Initialization and Acceptance Testing (Normal Operation) 4.7 Operating System Bootstrap VMB inherits a well defined environment and is responsible for further initialization. The following summarizes the operation of VMB. 1. Initialize a two-page SCB on the first-page boundary above VMB. 2. Allocate a three-page stack above the SCB. 3. Initialize the Restart Parameter Block (RPB). 4. Initialize the secondary bootstrap argument list. 5.
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System Initialization and Acceptance Testing (Normal Operation) 4.7 Operating System Bootstrap available (unmapped to other devices) for proper operation. After a successful bootstrap operation, control is passed to the secondary bootstrap image with the memory layout as shown in Figure 4–4. Figure 4–4 Memory Layout at VMB Exit 0 . Potential "bad" memory .
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System Initialization and Acceptance Testing (Normal Operation) 4.7 Operating System Bootstrap In the event that an operating system has an extraordinarily large secondary bootstrap which overflows the 128 KB of "good" memory, VMB loads the remainder of the image in memory above the "good" block. However, if there are not enough contiguous "good" pages above the block to load the remainder of the image, the bootstrap fails. 4.7.
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System Initialization and Acceptance Testing (Normal Operation) 4.7 Operating System Bootstrap Figure 4–5 Boot Block Format 31 24 23 BB-0: 1 16 15 n 0 any value low LBN high LBN (The next segment is also used as a PROM "signature block.
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System Initialization and Acceptance Testing (Normal Operation) 4.7 Operating System Bootstrap Note that it is not necessary that the boot image actually resides in PROM. Any boot image in Q22–bus memory space with a valid signature block on a 16 KB boundary is a candidate. Indeed, auxiliary bootstrap assumes that the image is in shared memory. The PROM image is copied into main memory in 127 page "chunks" until the entire PROM is moved.
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System Initialization and Acceptance Testing (Normal Operation) 4.7 Operating System Bootstrap Table 4–3 Network Maintenance Operations Summary Function Role Transmit Receive MOP Ethernet and IEEE 802.
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System Initialization and Acceptance Testing (Normal Operation) 4.7 Operating System Bootstrap Table 4–3 (Cont.) Network Maintenance Operations Summary Function Role Transmit Receive IEEE 802.3 Messages Server 5 IEEE TEST_RSP 5 in response to TEST_CMD 802.2 support of XID and TEST is limited to Class 1 operations.
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System Initialization and Acceptance Testing (Normal Operation) 4.7 Operating System Bootstrap Table 4–4 (Cont.
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System Initialization and Acceptance Testing (Normal Operation) 4.7 Operating System Bootstrap Table 4–4 (Cont.) Supported MOP Messages Message Type Message Fields LOOPBACK LOOP_DATA Skpcnt Skipped bytes bb-... Function 00-02 Forward data Forward addr ee-eeee-eeee-ee Data dd-... Skipped bytes bb-... Function 00-01 Reply Recpt # nn-nn Data dd-... nn-nn LOOPED_DATA Skpcnt nn-nn IEEE 802.
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System Initialization and Acceptance Testing (Normal Operation) 4.7 Operating System Bootstrap Because the request for load assistance is a MOP "must transact" operation, the network bootstrap continues indefinitely until a volunteer is found. The REQ_PROGRAM message is sent out in bursts of eight at four second intervals, the first four in MOP Version four IEEE 802.3 format and the last four in MOP Version 3 Ethernet format.
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System Initialization and Acceptance Testing (Normal Operation) 4.7 Operating System Bootstrap Table 4–5 MOP Multicast Addresses and Protocol Specifiers Function Address IEEE Prefix1 Protocol Owner Dump/Load AB-00-00-01-00-00 08-00-2B 60-01 Digital Remote console AB-00-00-02-00-00 08-00-2B 60-02 Digital Loopback assistance CF-00-00-00-00-002 08-00-2B 90-00 Digital 1 MOP 2 Not V4.0 only. used. 4.
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System Initialization and Acceptance Testing (Normal Operation) 4.8 Operating System Restart 7. Dispatch to the restart address, RPB$L_RESTART, with: SP Physical address of the RPB plus 512 AP Halt code PSL 041F0000 PR$_MAPEN 0 If the restart is successful, the operating system must clear CPMBX<3>(RIP). If restart fails, the firmware prints "Restart failure." on the system console. 4.8.1 Locating the RPB The RPB is a page-aligned control block which can be identified by the first three longwords.
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5 System Troubleshooting and Diagnostics This chapter provides troubleshooting information for the two primary diagnostic methods: online, interpreting error logs to isolate the FRU; and offline, interpreting ROM-based diagnostic messages to isolate the FRU. In addition, the chapter provides information on testing DSSI storage devices, using MOP Ethernet functions to isolate errors, and interpreting UETP failures.
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System Troubleshooting and Diagnostics 5.1 Basic Troubleshooting Flow • Incorrect bus node ID plugs In addition, check the following: • If you have received error notification using VAXsimPLUS, check the mail messages and error logs as described in Section 5.2. • If the operating system fails to boot (or appears to fail), check the console terminal screen for an error message. If the terminal displays an error message, see Section 5.3. • Check the LEDs on the device you suspect is bad.
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System Troubleshooting and Diagnostics 5.1 Basic Troubleshooting Flow If you change the system configuration, run the CONFIGURE utility at the console I/O prompt (>>>) to determine the CSR addresses and interrupt vectors recommended by Digital. These recommended values simplify the use of the MDM diagnostic package and are compatible with OpenVMS device drivers. You can select nonstandard addresses, but they require a special setup for use with OpenVMS drivers and MDM.
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System Troubleshooting and Diagnostics 5.2 Product Fault Management and Symptom-Directed Diagnosis In the case of Direct Memory Access (DMA) transactions where the NCA or NMC detects the error, the errors are typically signaled back to the CDAL-Bus device, but not posted to the NVAX CPU. In these cases the CDAL-Bus device typically posts a device level interrupt to the NVAX CPU via the NCA. In almost all cases, error state is latched by the NMC and NCA.
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System Troubleshooting and Diagnostics 5.2 Product Fault Management and Symptom-Directed Diagnosis • If the threshold has been exceeded for a particular type of cache error, mark a flag that will signify that this resource is to be disabled (the cache will be disabled in most, but not all, cases). • Update the SYSTAT software register with results of error/fault handling. • For memory uncorrectable Error Correction Code (ECC) errors: If machine check, mark page bad and attempt to replace page.
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System Troubleshooting and Diagnostics 5.2 Product Fault Management and Symptom-Directed Diagnosis A few other errors of the sort considered nonrecoverable are present. • Disable cache(s) permanently if error threshold is exceeded. • Flush and re-enable those caches which have been marked as good. • Clear the error flags. • Perform Return from Exception or Interrupt (REI) to recover and restart or continue the instruction stream for the following situations: Most INT54 errors.
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System Troubleshooting and Diagnostics 5.2 Product Fault Management and Symptom-Directed Diagnosis Table 5–1 OpenVMS Error Handler Entry Types OpenVMS Entry Type Code Description EMB$C_MC (002.) Machine Check Exception SCB Vector 4, IPL 1F EMB$C_SE (006.) Soft Error Interrupt Correctable ECC Memory Error SCB Vector 54, IPL 1A EMB$C_INT54 (026.) Soft Error Interrupt SCB Vector 54, IPL 1A EMB$C_INT60 (027.) Hard Error Interrupt 60 SCB Vector 60, IPL 1D EMB$C_POLLED (044.
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System Troubleshooting and Diagnostics 5.2 Product Fault Management and Symptom-Directed Diagnosis Figure 5–1 Event Log Entry Format 00 31 VMS Header Packet Revision Packet Header SYSTAT Subpacket Valid Flags Subpacket 1 . . . Subpacket n MLO-007263 Machine check exception entries contain, at a minimum, a Machine Check Stack Frame subpacket (Figure 5–2).
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System Troubleshooting and Diagnostics 5.2 Product Fault Management and Symptom-Directed Diagnosis Figure 5–2 Machine Check Stack Frame Subpacket 24 23 31 08 07 16 15 00 00000018 (hex) byte count (not including this longword, PC or PSL) AST LVL RN xxxxxx xx Mode Machine Check Code CPU ID xxxxxxxx 0. 4. ISTATE1 INT. SYS register 8. SAVEPC register 12. VA register 16. Q register 20. Opcode xxxxxxxx V R xxxxxxxx 24. ISTATE2 PC 28. PSL 32.
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System Troubleshooting and Diagnostics 5.2 Product Fault Management and Symptom-Directed Diagnosis Figure 5–3 Processor Register Subpacket 00 31 00 31 BPCR (IPR D4) 0. MMEADR (IPR E8) 92. PAMODE (IPR E7) 4. VMAR (IPR D0) 96. MMEPTE (IPR E9) 8. TBADR (IPR EC) 100. MMESTS (IPR EA) 12. PCADR (IPR F2) 104. PCSCR (IPR 7C) 16. BCEDIDX (IPR A7) 108. ICSR (IPR D3) 20. BCEDECC (IPR A8) 112. ECR (IPR 7D) 24. BCETIDX (IPR A4) 116. TBSTS (IPR ED) 28.
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System Troubleshooting and Diagnostics 5.2 Product Fault Management and Symptom-Directed Diagnosis Uncorrectable ECC memory error entries include a Memory subpacket (Figure 5–4). The memory subpacket consists of MEMCON, which is a software register containing the memory configuration and error status used for FRU isolation, and MEMCONn, the hardware register that matched the error address in MEAR. Figure 5–4 Memory Subpacket for ECC Memory Errors 00 31 MEMCON 0. MEMCONn (one longword from 2101.
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System Troubleshooting and Diagnostics 5.2 Product Fault Management and Symptom-Directed Diagnosis CURRENT ENTRY. MEMCON contains memory configuration information, but no error status as is done for the Memory subpacket. Figure 5–6 CRD Entry Subpacket Header 31 24 23 16 15 08 07 00 Logging Reason 0. Page Mapout CNT 4. MEMCON 8. Valid Entry CNT 12. Current Entry 16. MLO-007268 • Following the subpacket header are 1 to 16 fixed-length Memory CRD Entries (Figure 5–7).
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System Troubleshooting and Diagnostics 5.2 Product Fault Management and Symptom-Directed Diagnosis Figure 5–7 Correctable Read Data (CRD) Entry 31 24 23 16 15 08 07 00 Footprint 0. Status 4. CRD CNT 8. Pages Marked Bad CNT 12. First Event 16. Last Event 24. Lowest Address 32. Highest Address 36. MLO-007269 Each Memory CRD Entry represents one unique DRAM within the memory subsystem. A unique set, bank, and syndrome are stored in footprint to construct a unique ID for the DRAM.
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System Troubleshooting and Diagnostics 5.2 Product Fault Management and Symptom-Directed Diagnosis STATUS contains a record of the failure mode status of a particular DRAM over time. This in turn determines whether or not the CRD buffer is logged. For the first occurrence of an error within a particular DRAM, the memory location will be scrubbed (corrected read data is read, then written back to the memory location) and CRD CNT will be set to 1.
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System Troubleshooting and Diagnostics 5.2 Product Fault Management and Symptom-Directed Diagnosis The error log utility translates the entry into the traditional three-column format. The first column shows the register mnemonics, the second column depicts the data in hex, and the last column shows the actual English translations. As in the above example, the OpenVMS error handler also provides support for the /INCLUDE qualifier, such that CPU and MEMORY error entries can be selectively translated.
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System Troubleshooting and Diagnostics 5.2 Product Fault Management and Symptom-Directed Diagnosis To determine if any resources have been disabled, for example, if cache has been disabled for the duration of the OpenVMS session, examine the flags for the SYSTAT register in the packet header. In Example 5–1, a translation buffer data parity error latched in the TBSTS register caused a machine check exception error.
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System Troubleshooting and Diagnostics 5.2 Product Fault Management and Symptom-Directed Diagnosis Example 5–1 (Cont.) Error Log Entry Indicating CPU Error BPCR . . . TBSTS ECC80024 800001D3 LOCK SET TRANSLATION BUFFER DATA PARITY ERROR em_latch invalid s5 command = 1D(X) valid Ibox specifier ref. error stored . . . CESR . . . DSER . . .
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System Troubleshooting and Diagnostics 5.2 Product Fault Management and Symptom-Directed Diagnosis 5.2.6 Interpreting Memory Faults Using ANALYZE/ERROR If "memory subpacket" or "memory sbe reduction subpacket" is listed in the third column of the FLAGS register, there is a problem with one or more of the memory modules, CPU module, or backplane. • The "memory subpacket" message indicates an uncorrectable ECC error. Refer to Section 5.2.6.1 for instructions in isolating uncorrectable ECC error problems.
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System Troubleshooting and Diagnostics 5.2 Product Fault Management and Symptom-Directed Diagnosis # Examine the MEMCON software register ( ) under the memory subpacket. The MEMCON register provides memory configuration information. The OpenVMS error handler will mark each page bad and attempt page replacement, indicated in SYSTAT ( ). The DCL command SHOW MEMORY (Example 5–4) will also indicate the result of OpenVMS page replacement.
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System Troubleshooting and Diagnostics 5.2 Product Fault Management and Symptom-Directed Diagnosis Example 5–3 Error Log Entry Indicating Uncorrectable ECC Error V A X / V M S SYSTEM ERROR REPORT ******************************* ENTRY ERROR SEQUENCE 2. DATE/TIME 4-OCT-1991 09:14:29.86 SYSTEM UPTIME: 0 DAYS 00:01:39 SCS NODE: OMEGA1 COMPILED 6-NOV-1991 10:16:49 PAGE 25. 13. ******************************* LOGGED ON: SID 13001401 SYS_TYPE 03110A01 VAX/OpenVMS V5.5-2 INT54 ERROR KA52 CPU Microcode Rev # 1.
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System Troubleshooting and Diagnostics 5.2 Product Fault Management and Symptom-Directed Diagnosis Example 5–3 (Cont.) Error Log Entry Indicating Uncorrectable ECC Error MEMCON3 8B000003 64 bit mode Base address valid RAM size = 1MB base address = 0B(X) Example 5–4 SHOW MEMORY Display Under the OpenVMS Operating System $ SHOW MEMORY System Memory Resources on 21-FEB-1992 05:58:52.58 Physical Memory Usage (pages): Main Memory (128.
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System Troubleshooting and Diagnostics 5.
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System Troubleshooting and Diagnostics 5.2 Product Fault Management and Symptom-Directed Diagnosis The kernel performs memory scrubbing of DRAM memory cells that may flip due to transient alpha particles. Scrubbing simply reads the corrected data and writes it back to the memory location. Returning memory modules that only have SCRUBBED set in STATUS will cost the corporation money, since the repair centers will generally not find a problem.
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System Troubleshooting and Diagnostics 5.2 Product Fault Management and Symptom-Directed Diagnosis ( If CRD BUFFER FULL is set in LOGGING REASON ( ) (located in the subpacket header) or PAGE MAPOUT THRESHOLD EXCEEDED is set in SYSTAT ( ), the failing memory module should be replaced regardless of any thresholds.
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System Troubleshooting and Diagnostics 5.2 Product Fault Management and Symptom-Directed Diagnosis Example 5–6 Error Log Entry Indicating Correctable ECC Error V A X / V M S SYSTEM ERROR REPORT COMPILED 21-NOV-1991 16:55:58 PAGE 1. 1. ******************************* LOGGED ON: SID 13001401 SYS_TYPE 03110A01 ******************************* ENTRY ERROR SEQUENCE 2. DATE/TIME 27-SEP-1991 09:51:13.98 SYSTEM UPTIME: 0 DAYS 00:05:06 SCS NODE: OMEGA1 VAX/OpenVMS V5.
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System Troubleshooting and Diagnostics 5.2 Product Fault Management and Symptom-Directed Diagnosis Example 5–6 (Cont.) Error Log Entry Indicating Correctable ECC Error # STATUS CRD CNT MEMORY ERROR STATUS: _SIMM MEMORY MODULE: LOCATION 0A _set = 0 _bank = 0. ECC SYNDROME = 73(X) _CORRECTED DATA BIT = 0. 00000010 scrubbed 00000001 $ 1. PAGE MAPOUT CNT 00000000 0. FIRST EVENT 16B0F640 009622CB LAST EVENT 16B0F640 009622CB 16-OCT-1992 11:03:36.
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System Troubleshooting and Diagnostics 5.2 Product Fault Management and Symptom-Directed Diagnosis Example 5–7 Error Log Entry Indicating Q-Bus Error V A X / V M S SYSTEM ERROR REPORT ******************************* ENTRY ERROR SEQUENCE 1852. DATE/TIME 20-NOV-1991 14:26:11.14 SYSTEM UPTIME: 12 DAYS 20:04:19 SCS NODE: COMPILED 20-NOV-1991 14:28:13 PAGE 1. 75. ******************************* LOGGED ON: SID 13001401 SYS_TYPE 00310A01 VAX/OpenVMS V5.5-2 MACHINE CHECK KA52 CPU Microcode Rev # 1.
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System Troubleshooting and Diagnostics 5.2 Product Fault Management and Symptom-Directed Diagnosis Example 5–7 (Cont.) Error Log Entry Indicating Q-Bus Error BPCR . . . CESR . . . DSER . . . CIOEAR2 ECC80024 80000200 00000080 ! " 00001468 CP2 IO ERROR ERROR SUMMARY Q-22 BUS NXM # cp2 IO error address = 20001468 NDAL commander id (cp2 transac) = 0(X) . . . IPCR0 00000020 LOCAL MEMORY EXTERNAL ACCESS ENABLED ANAL/ERR/OUT=QBUS QBUS.ZPD 5.2.
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System Troubleshooting and Diagnostics 5.2 Product Fault Management and Symptom-Directed Diagnosis Example 5–8 Error Log Entry Indicating Polled Error V A X / V M S SYSTEM ERROR REPORT ******************************* ENTRY ERROR SEQUENCE 15. DATE/TIME 17-FEB-1992 05:22:00.90 SYSTEM UPTIME: 0 DAYS 00:27:48 SCS NODE: COMPILED 17-FEB-1992 05:32:21 PAGE 1. 2. ******************************* LOGGED ON: SID 13001401 SYS_TYPE 00310A01 VAX/OpenVMS V5.5-2 POLLED ERROR KA52 CPU Microcode Rev # 1.
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System Troubleshooting and Diagnostics 5.2 Product Fault Management and Symptom-Directed Diagnosis Example 5–8 (Cont.) Error Log Entry Indicating Polled Error MEMCON0 80000003 64 bit mode Base address valid RAM size = 1MB base address = 00(X) ANAL/ERR/OUT=TB1 TB1.
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System Troubleshooting and Diagnostics 5.2 Product Fault Management and Symptom-Directed Diagnosis Example 5–9 Device Attention Entry V A X / V M S SYSTEM ERROR REPORT ******************************* ENTRY ERROR SEQUENCE 15. DATE/TIME 17-FEB-1992 05:22:00.90 SYSTEM UPTIME: 0 DAYS 00:27:48 SCS NODE: COMPILED 17-FEB-1992 05:32:21 PAGE 1. 2. ******************************* LOGGED ON: SID 13001401 SYS_TYPE 00310A01 VAX/OpenVMS V5.5-2 DEVICE ATTENTION KA52 CPU Microcode Rev # 1. CONSOLE FW REV# 1.
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System Troubleshooting and Diagnostics 5.2 Product Fault Management and Symptom-Directed Diagnosis 5.2.9 VAXsimPLUS and System-Initiated Call Logging (SICL) Support Symptom-Directed Diagnostic (SDD) toolkit support for KA52/53/54 kernels is provided in version 2.0 of the toolkit. If version 2.0 is not available, you should install the previous version, as it provides support for many existing options. VAX 4000 systems use Symptom-Directed Diagnosis tools primarily for notification.
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System Troubleshooting and Diagnostics 5.
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System Troubleshooting and Diagnostics 5.2 Product Fault Management and Symptom-Directed Diagnosis Figure 5–9 shows the five VAXsimPLUS monitor screen displays. Table 5–3 provides a brief explanation of the five levels of screen displays. Table 5–3 Five-Level VAXsimPLUS Monitor Screen Displays Level Explanation 1. System The system level screen provides one box for each system being analyzed (in Figure 5–9 a single system is being analyzed).
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System Troubleshooting and Diagnostics 5.2 Product Fault Management and Symptom-Directed Diagnosis Using the theory of interpretation provided in the previous sections, you can manually interpret the error logs. Note The interpretation theory provided in this manual is also a STARS article and can be accessed via the Decoder Kit. (Theory 30B01.xxx reproduces in full, Section 5.2 of this manual). In summary, a service engineer should use VAXsimPLUS notification as follows: 1.
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System Troubleshooting and Diagnostics 5.2 Product Fault Management and Symptom-Directed Diagnosis $ ANALYZE/ERROR [binary filename] Example 5–10 SICL Service Request with Appended MEL File From: AB1X::SDD$MANAGER "VAXsimPLUS Message" 15-APR-1992 10:29:21.05 To: SYSTEM CC: Subj: SDD T2.0 Service Request - Analysis:[30B01.
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System Troubleshooting and Diagnostics 5.2 Product Fault Management and Symptom-Directed Diagnosis Also, if the system does not have dialout capability, you should answer no when asked if you want to enable SICL—if you enter yes, the system will attempt to send mail via DSNLink resulting in error messages. After VAXsimPLUS is installed you can activate SICL and customize the VAXsimPLUS mailing lists so that SICL messages are sent to an appropriate destination(s) on site.
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System Troubleshooting and Diagnostics 5.
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System Troubleshooting and Diagnostics 5.2 Product Fault Management and Symptom-Directed Diagnosis $ VAXSIM/FAULT SET PHONE 1-800-DIGITAL Finally, the VAXSIMPLUS/MERGE command is useful in examining how a device is functioning in a cluster. The merge command collects the messages that are being sent to the other CPUs in the cluster. 5.2.10 Repair Data for Returning FRUs When sending back an FRU for repair, include as much of the error log information as possible.
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System Troubleshooting and Diagnostics 5.3 Power-On Self-Test (POST) and ROM-Based Diagnostic (RBD) Failures " # $ % & ' Subtest log is two hex digits identifying, usually within 10 instructions, where in the diagnostic the error occurred. Loop_subtest_log is an additional log generated out of the current test specified by the current test number and subtestlog. Usually these logs occur in common subroutines called from a diagnostic test.
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System Troubleshooting and Diagnostics 5.3 Power-On Self-Test (POST) and ROM-Based Diagnostic (RBD) Failures Note Do not confuse the countdown pattern of powerup tests with the test number. In the following the last countdown was 58; this number should not be reported! The test number was 31. The countdown pattern is used to indicate progress in the power-up tests. The actual true test number associated with a countdown value can change from one release of the ROM code to another. For example: KA52-A T1.
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System Troubleshooting and Diagnostics 5.3 Power-On Self-Test (POST) and ROM-Based Diagnostic (RBD) Failures Table 5–4 shows the various LED values and console terminal displays as they point to problems in field-replaceable units (FRUs).
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System Troubleshooting and Diagnostics 5.3 Power-On Self-Test (POST) and ROM-Based Diagnostic (RBD) Failures Table 5–4 (Cont.
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System Troubleshooting and Diagnostics 5.3 Power-On Self-Test (POST) and ROM-Based Diagnostic (RBD) Failures Table 5–4 (Cont.
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System Troubleshooting and Diagnostics 5.3 Power-On Self-Test (POST) and ROM-Based Diagnostic (RBD) Failures Table 5–4 (Cont.
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System Troubleshooting and Diagnostics 5.
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System Troubleshooting and Diagnostics 5.3 Power-On Self-Test (POST) and ROM-Based Diagnostic (RBD) Failures Example 5–13 Failure Due to a Missing SIMM (One 16 Mbyte Set) KA52-A V1.2, VMB 2.14 Performing normal system tests. 72..71..70..69..68..67..66..65..64..63..62..61..60..59.. ? Test_Subtest_DC_88 Loop_Subtest=05 Err_Type=FF DE_NO_Memory_present.
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System Troubleshooting and Diagnostics 5.3 Power-On Self-Test (POST) and ROM-Based Diagnostic (RBD) Failures Example 5–14 Failure Due to a Missing SIMM (Two 16 Mbyte Sets) KA52-A T1.2-156, VMB 2.14 Performing normal system tests. 72..71..70..69..68..67..66..65..64..63..62..61..60..59..58.. ? Test_Subtest_31_06 Loop_Subtest=05 Err_Type=FF DE_Memory_Setup_CSRs.
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System Troubleshooting and Diagnostics 5.3 Power-On Self-Test (POST) and ROM-Based Diagnostic (RBD) Failures Example 5–15 Failure Due to a Bad SIMM KA52-A V1.2, VMB 2.14 Performing normal system tests. 72..71..70..69..68..67..66..65..64..63..62..61..60..59..58..57.. 56..55..54..53..52..51..50..49..48..47..46..45..44..43..42..41.. 40..39..38..37..36..35..34..33..32..31..30.. ? Test_Subtest_40_06 Loop_Subtest=00 Err_Type=FF DE_Memory_count_pages.lis 29..28..27..26..25..24..23..22..21..20..19..18..17..16..
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System Troubleshooting and Diagnostics 5.3 Power-On Self-Test (POST) and ROM-Based Diagnostic (RBD) Failures Example 5–16 SIMM Wrong Size Error: SIMM Set 1 (1E,1F,1G,1H), SSR = C14A SIMM_1E = 16MB SIMM_1F = 16MB SIMM_1G = 64MB ?? SIMM_1H = 16MB Memory Set 1: 01000000 to 01FFFFFF, 16MB, 32768 good pages, 0 bad pages ACTION: Replace SIMM 1G with one of the correct size. The diagnostics cannot always determine which SIMM caused a failure.
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System Troubleshooting and Diagnostics 5.3 Power-On Self-Test (POST) and ROM-Based Diagnostic (RBD) Failures parameter P4 set to 0 to rebuild the bitmap. To force rebuilding the bitmap to all good memory, enter the following commands: T 30 0 0 0 0 ; T 30 will not work by itself. T 0 ; rerun powerup script 5.4 Testing DSSI Storage Devices A DSSI storage device (ISE) may fail either during initial power-up or during normal operation.
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System Troubleshooting and Diagnostics 5.4 Testing DSSI Storage Devices If the ISE is connected to its front panel, you must install a bus node ID plug in the corresponding socket on the front panel. If the ISE is not connected to its front panel, it reads the bus node ID from the three-switch DIP switch on the side of the drive.
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System Troubleshooting and Diagnostics 5.4 Testing DSSI Storage Devices Example 5–17 Running DRVTST >>>SET HOST/DUP/DSSI/BUS:0 2 DRVTST Starting DUP server... Copyright (C) 1992 Digital Equipment Corporation Write/read anywhere on medium? [1=Yes/(0=No)] Return 5 minutes to complete. GAMMA::MSCP$DUP 17-MAY-1991 12:51:20 DRVTST CPU= GAMMA::MSCP$DUP 17-MAY-1991 12:51:40 DRVTST CPU= GAMMA::MSCP$DUP 17-MAY-1991 12:52:00 DRVTST CPU= . . . GAMMA::MSCP$DUP 17-MAY-1991 12:55:42 DRVTST CPU= Test passed. 0 00:00:09.
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System Troubleshooting and Diagnostics 5.4 Testing DSSI Storage Devices 5.4.1 Entering the DUP Driver Utility from Console Mode To examine and change DSSI parameters, you must first activate the DUP driver utility by setting host to the specific device for which you want to modify or examine parameters.
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System Troubleshooting and Diagnostics 5.5 Using MOP Ethernet Functions to Isolate Failures Unless the system is able to boot, the ‘‘Retrying network bootstrap’’ message will display every 8–12 minutes. Identify the system’s Ethernet circuit and circuit state, enter the SHOW KNOWN CIRCUITS command from the system conducting the test (system 2).
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System Troubleshooting and Diagnostics 5.5 Using MOP Ethernet Functions to Isolate Failures Instead of using the physical address, you could use the assistant node’s area address. When using the area address, system 3 is running the OpenVMS operating system. ***system 3*** $MCR NCP NCP>SHOW NODE KLATCH Node Volatile Summary as of 27-FEB-1992 21:04:11 Executor node = 25.900 (KLATCH) State Identification Active links = on = DECnet-VAX V5.4-1, OpenVMS V5.
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System Troubleshooting and Diagnostics 5.5 Using MOP Ethernet Functions to Isolate Failures ***system 2*** $ MCR NCP NCP>SET MODULE CONFIGURATOR CIRCUIT ISA-0 SURVEILLANCE ENABLED NCP>SHOW MODULE CONFIGURATOR KNOWN CIRCUITS STATUS TO ETHER.LIS NCP>EXIT $ TYPE ETHER.LIS Circuit name Surveillance flag Elapsed time Physical address Time of last report Maintenance version Function list Hardware address Device type = = = = = = = = = ISA-0 enabled 00:09:37 08-00-2B-28-18-2C 27-Feb 11:50:34 V4.0.
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System Troubleshooting and Diagnostics 5.6 Interpreting User Environmental Test Package (UETP) OpenVMS Failures 5.6.1 Interpreting UETP Output You can monitor the progress of UETP tests at the terminal from which they were started. This terminal always displays status information, such as messages that announce the beginning and end of each phase and messages that signal an error. The tests send other types of output to various log files, depending on how you started the tests.
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System Troubleshooting and Diagnostics 5.6 Interpreting User Environmental Test Package (UETP) OpenVMS Failures delete these log files yourself or rerun the entire UETP, which checks for old UETP.LOG files and deletes them. 5.6.1.2 Possible UETP Errors This section is intended to help you identify problems you might encounter running UETP.
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System Troubleshooting and Diagnostics 5.7 Using Loopback Tests to Isolate Failures While the test is running, the LED display on the console module should alternate between 6 and 3. A value of 6 latched in the display indicates a test failure. If the test fails, one of the following parts is faulty: the KA52/53 or the cabling. To test out to the end of the console terminal cable: 1. Plug the MMJ end of the console terminal cable into the back BA42B. 2.
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System Troubleshooting and Diagnostics 5.7 Using Loopback Tests to Isolate Failures >>>T 59 Reply Total Reply Total Reply Total . . . Reply Total >>> received from node: AA-00-04-00-FC-64 responses: 1 received from node: AA-00-04-00-47-16 responses: 2 received from node: 08-00-2B-15-48-70 responses: 3 received from node: AA-00-04-00-17-14 responses: 25 5.7.3 Q-Bus Option Loopback Testing Module self-tests run when you power up the system.
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System Troubleshooting and Diagnostics 5.
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6 FEPROM Firmware Update KA52/53/54 firmware is located on four chips, each 128 K by 8 bits of FLASH programmable EPROMs, for a total of 512 Kbytes of ROM. (A FLASH EPROM (FEPROM) is a programmable read-only memory that uses electrical (bulk) erasure rather than ultraviolet erasure.) FEPROMs provide nonvolatile storage of the CPU power-up diagnostics, console interface, and operating system primary bootstrap (VMB).
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FEPROM Firmware Update A Firmware Update Utility image consists of two parts, the update program and the new firmware, as shown in Figure 6–1. The update program uniformly programs, erases, reprograms, and verifies the entire FEPROM. Figure 6–1 Firmware Update Utility Layout Update Program New Firmware Image MLO-007271 Once the update has completed successfully, normal operation of the system may continue. The operator may then either halt or reset the system and reboot the operating system. 6.
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FEPROM Firmware Update 6.1 Preparing the Processor for a FEPROM Update Figure 6–2 W4 Jumper Setting for Updating Firmware Jumper MLO-009930 6.2 Updating Firmware via Ethernet To update firmware via the Ethernet, the ‘‘client’’ system (the target system to be updated) and the ‘‘server’’ system (the system that serves boot requests) must be on the same Ethernet segment. The Maintenance Operation Protocol (MOP) is the transport used to copy the network image.
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FEPROM Firmware Update 6.2 Updating Firmware via Ethernet NCP>SET CIRCUIT STATE ON Where is the system Ethernet circuit. Use the SHOW KNOWN CIRCUITS command to find the name of the circuit. Note The SET CIRCUIT STATE OFF command will bring down the system’s network. 3. Copy the file containing the updated code to the MOM$LOAD area on the server (this procedure may require system privileges). Refer to the Firmware Update Utility Release Notes for the Ethernet bootable filename.
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FEPROM Firmware Update 6.2 Updating Firmware via Ethernet Example 6–1 FEPROM Update via Ethernet ***** On Server System ***** $ MCR NCP NCP>SET CIRCUIT ISA-0 STATE OFF NCP>SET CIRCUIT ISA-0 SERVICE ENABLED NCP>SET CIRCUIT ISA-0 STATE ON NCP>EXIT $ $ COPY KA50_V41_EZ.SYS MOM$LOAD:*.* $ ***** On Client System ***** >>>b/100 eza0 (BOOT/R5:100 EZA0) 2.. Bootfile: ka50_v12 -EZA0 1..0..
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FEPROM Firmware Update 6.3 Updating Firmware via Tape 6.3 Updating Firmware via Tape To update firmware via tape, the system must have a TZ30, TF85, TK70, TK50 or TLZ04 tape drive. If you need to make a bootable tape, copy the bootable image file to a tape as shown in the following example. Refer to the release notes for the name of the file.
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FEPROM Firmware Update 6.3 Updating Firmware via Tape Example 6–2 FEPROM Update via Tape >>> BOOT/100 MKA500 (BOOT/R5:100 MKA500) 2.. Bootfile: KA50_V41_EZ -MKA500 1..0.. FEPROM update program ---CAUTION----- Executing this program will change your current FEPROM --Do you want to continue [Y/N] ? : y Blasting in V1.2-41. The program will take at most several minutes.
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FEPROM Firmware Update 6.4 FEPROM Update Error Messages Patchable Control Store (PCS) Loading Error Messages The following is a list of error messages that may appear if there is a problem with the PCS. The PCS is loaded as part of the power-up stream (before ROM-based diagnostics are executed). MESSAGE: CPU is not an NVAX COMMENT: CPU_TYPE as read in NVAX SID is not = 19 (decimal), as is should be for an NVAX processor.
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A Address Assignments A.1 KA52/53/54 General Local Address Space Map VAX Memory Space ---------------Address Range ----------------0000 0000 - 1FFF FFFF Contents -----------Local Memory Space (512MB) VAX I/O Space ------------Address Range ----------------2000 0000 - 2000 1FFF 2000 2000 - 2003 FFFF Contents -----------Local Q22-Bus I/O Space (8KB) Reserved Local I/O Space (248KB) 2008 0000 - 201F FFFF Local Register I/O Space (1.
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Address Assignments A.2 KA52/53/54 Detailed Local Address Space Map A.
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Address Assignments A.2 KA52/53/54 Detailed Local Address Space Map KA52/53/54 DETAILED LOCAL ADDRESS SPACE MAP (Cont.
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Address Assignments A.2 KA52/53/54 Detailed Local Address Space Map KA52/53/54 DETAILED LOCAL ADDRESS SPACE MAP (Cont.
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Address Assignments A.2 KA52/53/54 Detailed Local Address Space Map KA52/53/54 DETAILED LOCAL ADDRESS SPACE MAP (Cont.
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Address Assignments A.2 KA52/53/54 Detailed Local Address Space Map KA52/53/54 DETAILED LOCAL ADDRESS SPACE MAP (Cont.
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Address Assignments A.2 KA52/53/54 Detailed Local Address Space Map KA52/53/54 DETAILED LOCAL ADDRESS SPACE MAP (Cont.) ********************************************************************** The following addresses allow those KA52/53 Internal Processor Registers that are implemented in the SSC chip (External, Internal Processor Registers) to be accessed via the local I/O page. These addresses are documented for diagnostic purposes only and should not be used by non-diagnostic programs.
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Address Assignments A.2 KA52/53/54 Detailed Local Address Space Map KA52/53/54 DETAILED LOCAL ADDRESS SPACE MAP (Cont.) Local Register I/O Space (Cont.
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Address Assignments A.4 Global Q22–bus Address Space Map A.
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Address Assignments A.5 Processor Registers Table A–1 (Cont.
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Address Assignments A.5 Processor Registers Table A–1 (Cont.
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Address Assignments A.5 Processor Registers Table A–1 (Cont.
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Address Assignments A.5 Processor Registers Table A–1 (Cont.
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Address Assignments A.5 Processor Registers Table A–1 (Cont.
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Address Assignments A.5 Processor Registers Table A–1 (Cont.
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Address Assignments A.5 Processor Registers Table A–1 (Cont.
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Address Assignments A.5 Processor Registers Table A–1 (Cont.
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Address Assignments A.5 Processor Registers Table A–1 (Cont.
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Address Assignments A.5 Processor Registers Table A–1 (Cont.
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Address Assignments A.5 Processor Registers Table A–1 (Cont.
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Address Assignments A.6 IPR Address Space Decoding A.6 IPR Address Space Decoding Table A–2 IPR Address Space Decoding IPR Group Mnemonic2 IPR Address Range (hex) Contents 1 Normal 00000000..000000FF 256 individual IPRs. Bcache Tag BCTAG 01000000..011FFFE01 64k Bcache tag IPRs, each separated by 20(hex) from the previous one. Bcache Deallocate BCFLUSH 01400000..015FFFE01 64k Bcache tag deallocate IPRs, each separated by 20(hex) from the previous one. Pcache Tag PCTAG 01800000..
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B ROM Partitioning This section describes ROM partitioning and subroutine entry points that are public and are guaranteed to be compatible over future versions of the firmware. An entry point is the address at which any subroutine or subprogram will start execution. B.1 Firmware EPROM Layout The KA52/53/54 has 512 Kbytes of FEPROM. Unlike previous Q22–bus based processors, there is no duplicate decoding of the FEPROM into halt-protected and halt-unprotected spaces. The entire FEPROM is halt-protected.
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ROM Partitioning B.
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ROM Partitioning B.1 Firmware EPROM Layout B.1.1 System Identification Registers The firmware and operating system software reference two registers to determine the processor on which they are running. The first, the System Identification register (SID), is a NVAX internal processor register. The second, the System Identification Extension register (SIE), is a firmware register located in the FEPROM. B.1.1.1 PR$_SID (IPR 62) The SID longword can be read from IPR 62 using the MFPR instruction.
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ROM Partitioning B.1 Firmware EPROM Layout By convention, all VAX 4000 systems implement a longword at physical location 20040004 in the firmware FEPROM for the SIE. The layout of the SIE is shown in Figure B–3. A description of each field is provided in Table B–2.
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ROM Partitioning B.1 Firmware EPROM Layout All of the entry points are designed to run at IPL 31 on the interrupt stack in physcial mode. Virtual mode is not supported. Due to internal firmware architectural restrictions, users are encouraged to only call into the haltprotected entry points. These entry points are listed in Table B–3. Table B–3 Call-Back Entry Points CP$GET_CHAR_R4 20040008 CP$MSG_OUT_NOLF_R4 2004000C CP$READ_WTH_ PRMPT_R4 20040010 B.1.2.
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ROM Partitioning B.1 Firmware EPROM Layout B.1.2.2 CP$MSG_OUT_NOLF_R4 This routine outputs a message to the console. The message is specified either by a message code or a string descriptor. The routine distinguishes between message codes and descriptors by requiring that any descriptor be located outside of the first page of memory. Hence, message codes are restricted to values between 0 and 511. Registers R0,R1,R2,R3 and R4 are modified by this routine, all others are preserved.
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ROM Partitioning B.1 Firmware EPROM Layout A descriptor of the input string is returned in R0 and R1. R0 contains the length of the string and R1 contains the address. This routine inputs the string into the console program string buffer and therefore the caller need not provide an input buffer. Successive calls however destroy the previous contents of the input buffer. Registers R0 and R1 are modified by this routine, all others are preserved.
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ROM Partitioning B.1 Firmware EPROM Layout Figure B–4 Boot Information Pointers 20040018 Def Boot Dev Dscr Ptr Class Type Desc Length Boot Device String Ptr 2004001c Def Boot Flags Ptr ASCIZ Dev Name String Boot Flags (Longword) MLO-007701 The following macro defines the boot device descriptor format. ;------------------------------------------------------------; Default Boot Device Descriptor ; boot_device_descriptor:: base = . . = base + dsc$w_length .word nvr$s_boot_device .
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C Data Structures and Memory Layout This appendix contains definitions of the key global data structures used by the CPU firmware. C.1 Halt Dispatch State Machine The CPU halt dispatcher determines what actions the firmware will take on halt entry based on the machine state. The dispatcher is implemented as a state machine, which uses a single bitmap control word and the transition (see Table C–1) to process all halts.
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Data Structures and Memory Layout C.1 Halt Dispatch State Machine 11 : halt • User Action, specified with the SET HALT console command.
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Data Structures and Memory Layout C.1 Halt Dispatch State Machine Table C–1 (Cont.
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Data Structures and Memory Layout C.1 Halt Dispatch State Machine Table C–1 (Cont.
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Data Structures and Memory Layout C.1 Halt Dispatch State Machine Table C–1 (Cont.
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Data Structures and Memory Layout C.2 Restart Parameter Block Table C–2 (Cont.) Restart Parameter Block Fields (R11)+ Field Name Description 10: RPB$L_HALTPC R10 on entry to VMB (HALT PC). 10: RPB$L_HALTPSL PR$_SAVPSL on entry to VMB (HALT PSL). 18: RPB$L_HALTCODE AP on entry to VMB (HALT CODE). 1C: RPB$L_BOOTR0 R0 on entry to VMB.
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Data Structures and Memory Layout C.2 Restart Parameter Block Table C–2 (Cont.) Restart Parameter Block Fields (R11)+ Field Name Description 44: RPB$Q_PFNMAP The PFN bitmap is an array of bits, where each bit has the value "1" if the corresponding page of memory is valid, or has the value "0" if the corresponding page of memory contains a memory error. Through use of the PFNMAP, the operating system can avoid memory errors by avoiding known bad pages altogether.
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Data Structures and Memory Layout C.2 Restart Parameter Block Table C–2 (Cont.) Restart Parameter Block Fields (R11)+ Field Name Description Note 1. For VAX/OpenVMS, the RPB$T_FILE must contain the root directory string "SYSn." on a non-network bootstrap. This string is parsed by SYSBOOT (SYSBOOT does not use the high nibble of BOOTR5). 2. The RPB$T_FILE is overwritten to contain the boot node name for compatibility with ELN VX.X (this field is only initialized this way when performing a network boot).
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Data Structures and Memory Layout C.2 Restart Parameter Block Table C–2 (Cont.) Restart Parameter Block Fields (R11)+ Field Name Description 108: RPB$B_CTRLLTR Boot device controller number biased by 1. In VAX/OpenVMS, this field is used by INIT (in SYS) to construct the boot device’s controller letter. A 0 implies this field has not been initialized, else if initialized, A=1, B=2, etc. (this field was added in Version 13 of VMB). nn: The rest of the RPB is zeroed. C.
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Data Structures and Memory Layout C.3 VMB Argument List Table C–3 (Cont.) VMB Argument List (AP)+ Field Name Description 34: VMB$Q_NODENAME Boot node name which is initialized when performing a network boot. This field is copied from the Target System Name parameter of the parameters message. 3C: VMB$Q_HOSTADDR Host node address (this value is only initialized when booting over the network). This field is copied from the Host System Address parameter of the parameters message.
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D Configurable Machine State The KA52/53/54 CPU modules have many control registers that need to be configured for proper operation of the module. The following list shows the normal state of all configurable bits in the CPU module as they are left after the successful completion of power-up ROM diagnostics.
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Configurable Machine State 8: 7: 6: 5: 4: 3: 2: 1: 0: ICCS: IO2 ID enable 1 = enabled Force wrong CP2 bus parity - off - diagnostic use only Force wrong CP1 bus parity - off - diagnostic use only Force wrong NDAL master parity - off - diagnostic use only Force wrong NDAL slave parity - off - diagnostic use only Enable prefetch 1 = enable CP bus prefetch on DMA reads Force write buffer hit - off - diagnostic use only Force CP2 bus owner - diagnostic use only 0 = disabled Force CP1 bus owner - diagnostic us
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Configurable Machine State 29: Diagnostic Checkbit mode 0 = disabled* - diagnostic use only 28: QBus on I01 0 = QBus on IO2* 27: Enable soft error log (NDAL & memory related) 0 = disabled* - OpenVMS enables this 26: Flush BCache 0 = don’t flush* 24:17: Memory diagnostic check bits (0*) - may not be read as 0 8:7: NDAL Timeout Scaler 00 = 2600 cycles* - maximum to preserve timeout order 6: Disable memory error 0 = memory errors deteted and corrected* 5: Refresh interval timer select 0 = 328 cyc
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Configurable Machine State 31:24: CPU type - 13hex (NVAX code) 13:8: Patch revision 7:0: Microcode revision ICSR: IBox Control and Status Register (IPR D3) 0: VIC enable 1 = enabled ECR: EBox Control Register (IPR 7D) 13: FBox test enable 0 = disable* - diagnostic use only 7: Interval time mode 1 = full CPU implemented interval timer 5: S3 stall timeout 0 = counts cycles w/ timeout_enable asserted (~3 sec)* 3: FBox stage 4 bypass 1 = enabled - improves FBox latency 2: S3 external time base timeou
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Configurable Machine State 0: CCTL: D_enable 1 = enable PCache for INVAL, D-stream read/write/fill CBox Control Register (IPR A0) 30: Software ETM 0 = disabled* - diagnostic use only 16: Force NDAL parity error - off - diagnostic use only 15:11: Performance monitoring bits (0*) - diagnostic use only CQBIC: -----SCR: 10: Disable CBox write packer 0 = write packer enabled* - improves write latency 9: Read timeout time base 0 = external time base 8: Software ECC 0 = use correct ECC* 7: Disable BC
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Configurable Machine State ICR: QBMBR: Interprocessor Communication Register (2000 1F40) 8: AUX Halt 0 = no halt - AUX mode not supported 6: ICR interrupt enable 0 = interprocessor interrupts disabled - only uniprocessor config.
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Configurable Machine State NICSR6: Command and Mode Register (2000 8018) 30: Interrupt enable 0 = disabled* 28:25: Burst limit mode maximum number of longwords transferred in a single DMA burst. 1*,2,4,8 when NICSR<19>is clear; 1*,4 when set.
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Configurable Machine State 23: ROM access time 0 = 350 ns* 22:20: ROM size 110 = 512KB 18:16: Halt protected space 110 = 20040000 - 200BFFFF (historical) 15: n/a 14:12: n/a 6: Programmable address strobe 1 ready enable (for BDR) 1 = ready asserted after address strobe 5:4: Programmable address strobe 1 enable (for BDR) 11 = read enabled, write enabled 2: Programmable address strobe 0 ready enable 0 = no ready after address strobe* Used for FEPROM 1:0: Programmable address strobe 0 enable 00 = re
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Configurable Machine State T1CR: Programmable Timer 1 Control Register (2014 0110) 6: Interrupt enable 0 = disabled* 2: STP 0 = run after overflow* 0: RUN 1 = counter incrementing every microsecond (historical) TNIR: Programmable Timer Next Interval Registers (2014 0108, 2014 0118) 31:0: Timer next interval count (use 2’s complement) range = 0* to 1.
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E NVRAM Partitioning This appendix describes how the CPU firmware partitions the SSC 1 KB battery-backed-up (BBU) RAM. E.1 SSC RAM Layout The KA52/53/54 firmware uses the 1K byte of NVRAM on the SSC (see Figure E–1), for storage of firmware specific data structures and other information that must be preserved across power cycles. This NVRAM resides in the SSC chip starting at address 20140400. The NVRAM should not be used by the operating systems except as documented below.
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NVRAM Partitioning E.1 SSC RAM Layout E.1.1.1 Console Program MailBoX (CPMBX) The Console Program MailBoX (CPMBX) comprised of NVR0, is a software data structure located at the beginning of NVRAM (20140400). The CPMBX is used to pass information between the CPU firmware and diagnostics, VMB, or an operating system.
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NVRAM Partitioning E.1 SSC RAM Layout Table E–2 Bit Functions for NVR1 Field Name Description 2 MCS If set, indicates that the attached terminal supports Multinational Character Set. If clear, MCS is not supported. 1 CRT If set, indicates that the attached terminal is a CRT. If clear, indicates that the terminal is hardcopy. E.1.1.
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F MOP Counters The following counters are kept for the Ethernet boot channel. All counters are unsigned integers. V4 counters rollover on overflow. All V3 counters "latch" at their maximum value to indicate overflow. Unless otherwise stated, all counters include both normal and multicast traffic. Furthermore, they include information for all protocol types. Frames received and bytes received counters do not include frames received with errors.
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MOP Counters Table F–1 (Cont.) MOP Counter Block V3 V4 Name Off Len Off Len Description Rx_BYTES 02 4 10 8 Bytes received. The total number of user data bytes successfully received. This does not include Ethernet data link headers. This number is the number of bytes in the Ethernet data field, which includes any padding or length fields when they are enabled. These are bytes from frames that passed hardware filtering.
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MOP Counters Table F–1 (Cont.) MOP Counter Block V3 V4 Name Off Len Off Len Description Rx_FRAMES 0A 4 20 8 Frames received. The total number of frames successfully received. These are frames that passed hardware filtering. Provides a gross measurement of incoming Ethernet usage by the local system. Provides information used to determine the ratio of the error counters to successful transmits. Tx_FRAMES 0E 4 28 8 Frames sent. The total number of frames successfully transmitted.
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MOP Counters Table F–1 (Cont.) MOP Counter Block V3 V4 Name Off Len Off Len Description Tx_INIT_DEFFERED 1A 4 40 8 Frames sent1 , initially deferred. The total number of times that a frame transmission was deferred on its first transmission attempt. In conjunction with total frames sent, measures Ethernet contention with no collisions. Tx_ONE_COLLISION 1E 4 48 8 Frames sent 1 , single collision.
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MOP Counters Table F–1 (Cont.) MOP Counter Block V3 V4 Name Off Len Off Len Description TxFAIL_COUNT 26 2 - - Send failure count2 . The total number of times a transmit attempt failed. Each time the counter is incremented, a type of failure is recorded. When Readcounter function reads the counter, the list of failures is also read. When the counter is set to zero, the list of failures is cleared. In conjunction with total frames sent, provides a measure of significant transmit problems.
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MOP Counters Table F–1 (Cont.) MOP Counter Block V3 V4 Name Off Len Off Len Description TxFAIL_CARIER_CHECK - - 60 8 Send failure—Carrier check failed. The data link did not sense the receive signal that is required to accompany the transmission of a frame. Indicates a failure in either the transmitting or receiving hardware. Could be caused by either transceiver, transceiver cable, or a babbling controller that has been cut off. TxFAIL_SHRT_CIRCUIT - - 68 8 Send failure—Short circuit3 .
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MOP Counters Table F–1 (Cont.) MOP Counter Block V3 V4 Name Off Len Off Len Description TxFAIL_REMOTE_DEFER - 80 8 Send failure—Remote failure to defer3 . A remote system began transmitting after the allowed window for collisions. This indicates either a problem with some other system’s carrier sense or a weak transmitter. RxFAIL_COUNT 2A 2 - - Receive failure count2 . The total number of frames received with some data error.
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MOP Counters Table F–1 (Cont.) MOP Counter Block V3 V4 Name Off Len Off Len Description RxFAIL_FRAMING_ERR - - 90 8 Receive failure—Framing error. The frame did not contain an integral number of 8 bit bytes. This indicates several possible failures, such as EMI, late collisions, or improperly set hardware parameters. RxFAIL_LONG_FRAME - - 98 8 Receive failure—Frame too long3 . The frame was discarded because it was outside the Ethernet maximum length and could not be received.
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MOP Counters Table F–1 (Cont.) MOP Counter Block V3 V4 Name Off Len Off Len Description NO_SYSTEM_BUFFER 32 2 B0 8 System buffer unavailable3 . The total number of times no system buffer was available for an incoming frame. In conjunction with total frames received, provides a measure of system buffer related receive problems. The problem reflected in this counter is also captured as an event. This can be any buffer between the hardware and the user buffers (those supplied on Receive requests).
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G Error Messages The error messages issued by the KA52/53/54 firmware fall into three categories: halt code messages, VMB error messages, and console messages. G.1 Machine Check Register Dump Some error conditions, such as machine check, generate an error summary register dump preceding the error message.
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Error Messages G.2 Halt Code Messages The number preceding the halt message is the "halt code." This number is obtained from SAVPSL<13:8>(RESTART_CODE), IPR 43, which is saved on any processor restart operation. Table G–1 HALT Messages Code Message Description ?02 EXT HLT External halt, caused by either console BREAK condition, Q22–bus BHALT_L, or DBR bit was set while enabled. _03 — Power-up, no halt message is displayed.
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Error Messages G.2 Halt Code Messages Table G–1 (Cont.) HALT Messages Code Message Description PSL EXC6 1 PSL<26:24> = 6 on interrupt or exception. ?1B PSL EXC7 1 PSL<26:24> = 7 on interrupt or exception. ?1D PSL REI51 ?1E PSL REI6 1 PSL<26:24> = 6 on an REI instruction. ?1F PSL REI7 1 PSL<26:24> = 7 on an REI instruction. ?3F MICROVERIFY FAILURE ?1A PSL<26:24> = 5 on an REI instruction Microcode power-up self-test failed.
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Error Messages G.3 VMB Error Messages Table G–2 (Cont.) VMB Error Messages Code Message Description ?4C DEVINACT Failed to initialize boot device. ?4D DEVOFFLINE Device is offline. ?4E MEMERR Memory initialization error. ?4F SCBINT Unexpected SCB exception or machine check. ?50 SCB2NDINT Unexpected exception after starting program image. ?51 NOROM No valid ROM image found. ?52 NOSUCHNODE No response from load server. ?53 INSFMAPREG The Q22–bus map initialization failed.
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Error Messages G.4 Console Error Messages Table G–3 (Cont.) Console Error Messages Code Message Description ?67 VALUE TOO LARGE The value specified does not fit in the destination. ?68 QUALIFIER CONFLICT Qualifier conflict; for example, two different data sizes are specified for an EXAMINE command. ?69 UNKNOWN QUALIFIER The switch is unrecognized. ?6A UNKNOWN SYMBOL The symbolic address in an EXAMINE or DEPOSIT command is unrecognized.
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Error Messages G.4 Console Error Messages Table G–3 (Cont.) Console Error Messages Code Message Description ?7E CONSOLE STACK OVERRUN SSC RAM stack overflowed into NVR. ?7F COMMAND NOT SUPPORTED Command on similar modules not supported on this product. ?80 ILLEGAL PASSWORD Password is not 16 characters in length. ?81 INCORRECT PASSWORD Password entered does not match previously entered password. ?82 PASSWORD FACILITY NOT ENABLED A password has not been set.
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H Related Documents The following documents contain information relating to the maintenance of systems that use the KA52 CPU module.
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Related Documents Title Part Number1 VAX 4000 Model 105A/106A Troubleshooting and Diagnostics Information EK–515AA–TS 1# = current revision, which is always shipped. The following documents contain information relating to the maintenance of systems that use either the KA52, KA53 or the KA54 CPU module.
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Glossary ASCII American standard code for information interchange. BFLAG Boot FLAG is the longword supplied in the SET BFLAG and BOOT /R5: commands that qualify the bootstrap operation. SHOW BFLAG displays the current value. BHALT Q22–bus Halt signal is usually tied to the front panel Halt switch. BIP Boot In Progress flag in CPMBX<2> Bootstrap A link between console mode (the system firmware) and programming mode (the operating system).
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CPMBX Console Program Mailbox is used to pass information between operating systems and the firmware. CRC Character code recognition. The use of pattern recognition techniques to identify characters by automatic means. CQBIC CVAX to Q22–bus interface chip. CSR Control status register. A register used to control the operation of a device and record the status of an operation or both. CPU Central processing unit.
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ECC Error Correction Code. Code that carries out automatic error correction by performing an exclusive "or" operation on the transferred data and applying a correction mask. Factory Installed Software (FIS) Operating system software loaded into a system disk during manufacture. On site, the FIS is bootstraped in the system, prompting a predefined menu of questions on the final configuration. FEPROM Flash Erasable Programmable Read-Only Memory (FEPROM).
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IPR Internal Processor Registers implemented by the processor chip set. These longword registers are only accessible with the instructions MTPR (Move To Processor Register) and MFPR (Move From Processor Register) and require kernel mode privileges. This document uses the prefix "PR$_" when referencing these registers. ISE Integrated storage element. An intelligent disk drive used on the Digital Storage Systems Interconnect. IT Interval timer. LED Light emitting diode.
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NVR Nonvolatile random access memory. A memory device that retains information in the absence of power. NVRAM Nonvolatile RAM. On the KA52/53, this is 1 Kb of battery backed-up RAM on the SSC. PC Program Counter or R15. PCB Process Control Block is a data structure pointed to by the PR$_PCBB register and contains the current process’ hardware context. PFN Page Frame Number is an index of a page (512 bytes) of local memory. A PFN is derived from the bit field <23:09> of a physical address.
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PR$_SAVPC SAVed Program Counter, IPR 42. PR$_SAVPSL SAVed Program Status Longword, IPR 43. PR$_SCBB System Control Block Base register, IPR 17. PR$_SISR Software Interrupt Summary Register, IPR 21. PR$_TODR Time Of Day Register, IPR 27, is commonly referred to as the Time Of Year register or TOY clock. PR$_TXCS T(X)ransmit Console Status, IPR 34. PR$_TXDB T(X)ransmit Data Buffer, IPR 35. PROM Programmable read-only memory. A read-only memory device that can be programmed.
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QNA Q22–bus Ethernet controller module. RAM Random access memory. A read/write memory device. RAP Register address port. RIP Restart In Progress flag in CPMBX<3>. ROM Read-only memory. A memory device that cannot be altered during the normal use of the computer. RPB Restart parameter block. SCB System Control Block. A data structure pointed to by PR$_SCBB. It contains a list of longword exception and interrupt vectors. SCSI Small computer system interface.
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SP Stack pointer. An address location that contains the address of the processordefined stack. The processor-defined stack is an area of memory set aside for temporary storage or for procedure and interrupt service linkages. SRM Standard Reference Manual, as in VAX SRM. SSC System Support Chip. TOY Time of year. VAXcluster configuration A highly integrated organization of OpenVMS systems that communicate over a high-speed communications path.
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Index A Acceptance testing, 4–14 to 4–17 Algorithm to find a valid RPB, 4–35 to restart operating system, 4–34 ANALYZE/ERROR, 5–14 interpreting CPU errors using, 5–15 interpreting DMA to host transaction faults using, 5–28 interpreting memory errors using, 5–18 interpreting system bus faults using, 5–26 ANALYZE/SYSTEM, 5–21 Asynchronous communications interfaces support for, 2–6 Asynchronous communications options list of, 2–6 B Binary load and unload (X command), 3–34 Bits RPB$V_DIAG, 4–28 RPB$V_SOLICT, 4
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Console commands (cont’d) EXAMINE, 3–15 FIND, 3–16 HALT, 3–17 HELP, 3–17 INITIALIZE, 3–19 keywords, 3–9 list of, 3–10 MOVE, 3–20 NEXT, 3–21 qualifier and argument conventions, 3–3 qualifiers, 3–8 REPEAT, 3–23 SEARCH, 3–24 SET, 3–25 SHOW, 3–27 START, 3–30 symbolic addresses, 3–4 syntax, 3–3 TEST, 3–30 UNJAM, 3–34 X (binary load and unload), 3–34 Console error messages sample of, 5–41 Console I/O mode special characters, 3–1 Console port, testing, 5–61 Console security feature values, 3–26 CONTINUE command, 3
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G General purpose registers (GPRs) symbolic addresses for, 3–4 H H3103 loopback connector, 5–62 H8572 loopback connector, 5–62 Halt dispatch, C–1 HALT on bootstrap failure, 4–24 HALT command, 3–17 Halt protection, override, 5–48 HELP command, 3–17 I Indicators function of, 1–6 identification of, 1–5 INIT, 4–21 Initial power-up test See IPR Initialization following a processor halt, 4–34 prior to bootstrap, 4–21 INITIALIZE command, 3–19 Internal mass storage devices list of, 2–2 IPL_31, 4–22 iSYS$TEST logi
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Memory (cont’d) expansion of, 1–9 isolating FRU, 4–15, 5–48 rules for adding, 1–9 testing, 5–48 Memory configuration KA52/53/54 system, 2–1 Memory modules, 1–9 Memory option installation of, 1–11 Memory test, 1–12 Module self-tests, 4–6, 5–63 MOM$LOAD, 4–28 MOP functions, 4–29 MOP program load sequence, 4–28 MOP, functions, 5–56 MOVE command, 3–20 MS44 memory modules, 1–9 N Network listening, 4–33 NEXT command, 3–21 NVRAM CPMBX, E–2 partitioning, E–1 O OLDUETP.
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Related documents, H–1 REPEAT command, 3–23 REQ_PROGRAM, 4–33 Restart, 4–34 Restart Parameter Block (RPB) RIP flag, 4–34 RF-series ISE diagnostics, 4–7, 5–53 errors, 5–53 RF-series ISE local programs list of, 5–54 ROM-based diagnostics, 4–7 to 4–12 console displays during, 5–41 isolating failures with, 5–44 list of, 4–8 parameters, 4–8 utilities, 4–8 RPB initialization, C–5 locating, 4–35 RPB Signature Format, 4–35 S Scripts, 4–12 list of, 4–13 SCSI ID assignments recommendations for, 2–6 SEARCH command, 3
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VAXsimPLUS, 5–3, 5–32 customizing, 5–39 enabling SICL, 5–40 installing, 5–38 Virtual Memory Boot (VMB), 4–24 definition of, 4–23 primary bootstrap, 4–23 secondary bootstrap, 4–26 Index–6 W Warmstart, 4–34 X X command (binary load and unload), 3–34
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Reader’s Comments VAX 4000 Model 100, 100A, 105A, 106A KA52/53/54 CPU System Maintenance EK–473AB–MG. C01 Your comments and suggestions help us improve the quality of our publications. Thank you for your assistance.
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