Specifications

Data Structures
1.2 Adapter Control Block (ADP)
Table 1–2 (Cont.) Contents of Adapter Control Block
Field Name Contents
For both types of VAX processor, adapter dispatch table entries that
correspond to unused vectors contain the address of the adapter’s
unexpected-interrupt service routine.
ADP$L_DPQFL* Data path wait queue forward link. IOC$REQDATAP and IOC$RELDATAP
read and write this field. When a driver fork process requests a buffered
data path and none is currently available, IOC$REQDATAP saves driver
context in the device’s UCB fork block, inserts the fork block address in the
data path wait queue, and suspends the driver fork process.
When another driver calls IOC$RELDATAP to release a buffered data path,
the routine dequeues a UCB fork block address from the data path wait
queue, allocates a data path to the driver, and reactivates that driver fork
process.
This field is also known as ADP$L_MBASCB. For MASSBUS adapters and
generic VAXBI adapters, the system adapter initialization routine stores
the address of the adapter’s interrupt vector in this field. Certain power
failure recovery operations use the contents of ADP$L_MBASCB to refresh
the SCB vectors. The actual stored value is CRB$L_INTD+1, the set low bit
of the address indicating that the interrupt stack is to be used in servicing
interrupts.
ADP$L_DPQBL* Data path wait queue backward link. IOC$REQDATAP and
IOC$RELDATAP read and write this field.
This field is also known as ADP$L_MBASPTE. For generic VAXBI adapters,
the system adapter initialization routine stores here the contents of the
first of 16 SPTEs that map the adapter’s node space. For the MASSBUS
adapter, the routine stores here the SPTE value that maps MBA address
space. Certain recovery operations use the contents of ADP$L_MBASPTE to
restore SPTE values and remap node space following a power failure.
ADP$L_AVECTOR* Address of first SCB vector for adapter.
ADP$L_BI_IDR* Longword mask specifying, by a single set bit, which VAXBI node is the
destination of interrupts from this adapter. In VAX 82x0/83x0 systems, the
VAXBI node of the primary processor becomes the destination for interrupts;
in VAX 85x0/8700/88x0 and VAX 6000-series systems, it is the VAXBI
node at which the memory-interconnect-to-VAXBI adapter (NBIB, PBIB,
or DWMBA/B) resides.
ADP$W_BI_FLAGS* VAXBI device flags field.
ADP$W_BI_VECTOR* Offset of the first interrupt vector for this VAXBI node from the start of its
SCB page. ADP$L_AVECTOR contains the address of this vector.
ADP$L_SCB_PAGE* Offset to SCB page for this VAXBI device.
ADP$L_BIMASTER* Address of the ADP of the master device of the VAXBI (for example, the
DWMBA in a VAX 6000-series system).
ADP$W_ADPDISP_
FLAGS*
Flags used by the ADPDISP macro to control branching according to
adapter characteristics. The following bit fields are defined within ADP$W_
ADPDISP_FLAGS:
ADP$V_ADPDISP_INIT ADPDISP flags have been initialized
ADP$V_ADAP_MAPPING Adapter mapping supported
(continued on next page)
1–8